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The Relatively Simple Cpu Simulator

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Conference

2001 Annual Conference

Location

Albuquerque, New Mexico

Publication Date

June 24, 2001

Start Date

June 24, 2001

End Date

June 27, 2001

ISSN

2153-5965

Page Count

9

Page Numbers

6.1030.1 - 6.1030.9

Permanent URL

https://peer.asee.org/9728

Download Count

1869

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Paper Authors

author page

John Carpinelli

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1420

The Relatively Simple CPU Simulator

John D. Carpinelli New Jersey Institute of Technology

Abstract

The Relatively Simple CPU Simulator is an instructional aid for students studying computer architecture and CPU design, typically at the junior or senior level. It simulates the Relatively Simple CPU, a 16-instruction processor introduced in the textbook Computer Systems Organization and Architecture1. Students first enter an assembly language program, which is assembled by the simulator. After correcting any syntax errors, the user simulates the fetch, decode, and execute cycles for each instruction in the program. The user may simulate the execution of the program by clock cycle, by instruction, using breakpoints, or as a single, continuous execution.

The simulator uses animation to give students a more intuitive understanding of how the CPU fetches, decodes, and executes instructions. It shows the flow of data within the CPU’s register section. A pop-up window animates data flow within the ALU whenever it is active. The control unit highlights signals asserted by the control unit and used in the rest of the CPU. Users may select either a hard-wired or microcoded control unit.

The Relatively Simple CPU simulator is coded as a platform-independent Java applet that can be executed within any Java-enabled web browser. The simulator and its source code are freely available under the GNU Public License.

1. Introduction

The goal of this simulation package is to actively engage students in the process of learning how a CPU works. Students who take a passive approach to learning are less likely to learn the material and are less likely to perform well in their courses. By illustrating the flow of data within a CPU as it fetches, decodes, and executes instructions, this simulator will help students to learn the material better.

Most textbooks for computer organization and architecture have some type of simulator available2,3,4. (One notable exception5 does not offer a simulator.) However, these simulators only accept program input and output results, such as the contents of registers after each instruction. They show students what happens within a computer, but not the actions that cause each operation

Proceedings of the 2001 American Society for Engineering Education Annual Conference & Exposition Copyright  2001, American Society for Engineering Education

Carpinelli, J. (2001, June), The Relatively Simple Cpu Simulator Paper presented at 2001 Annual Conference, Albuquerque, New Mexico. https://peer.asee.org/9728

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