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Translating the Instructional Processor from VHDL to Verilog

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2018 ASEE Annual Conference & Exposition


Salt Lake City, Utah

Publication Date

June 23, 2018

Start Date

June 23, 2018

End Date

July 27, 2018

Conference Session

COED: EE Topics

Tagged Division

Computers in Education

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Paper Authors


Ronald J. Hayne The Citadel

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Ronald J. Hayne is an Associate Professor in the Department of Electrical and Computer Engineering at The Citadel. He received his B.S. in Computer Science from the United States Military Academy, his M.S. in Electrical Engineering from the University of Arizona, and his Ph.D. in Electrical Engineering from the University of Virginia. Dr. Hayne's professional areas of interest include digital systems design and hardware description languages. He is a retired Army Colonel with experience in academics and Defense laboratories.

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Translating the Instructional Processor from VHDL to Verilog


An Instructional Processor has been developed for use as a design example in an Advanced Digital Systems course. The system was originally modeled in VHDL and was simulated using Xilinx design tools to demonstrate operation of the processor. The design model can also be synthesized and implemented in hardware on a field programmable gate array (FPGA). The goal of this project was to translate the Instructional Processor into the Verilog hardware description language, while maintaining the same operational characteristics.

VHDL and Verilog are IEEE standard languages used for the development, verification, synthesis, and testing of hardware designs. While their language reference manuals specify the formal syntax used to model designs, they should not be mistaken for simple programming languages. Used correctly, these languages describe hardware constructs, which can be implemented using computer aided design tools. These synthesis tools have their own design guidelines, which align modelling techniques with standard library modules such as multiplexers, decoders, registers, and memory.

Keeping the focus on modelling hardware, rather than variations in syntax, the languages are more similar than different. Concurrent combinational logic, such as an arithmetic logic unit (ALU) or multiplexer, can be implemented using language specific signal assignment statements. Both languages can also model clock triggered sequential logic, such as a register or counter, using process or block statements. In addition, both VHDL and Verilog support design abstraction using behavioral or structural modelling constructs.

The process of translating the Instructional Processor from VHDL to Verilog has also resulted in several key insights and lessons learned. These range from correct use of signal types and library functions to important differences in simulation versus synthesis tools. For example, a memory module that was verified during simulation was left uninitialized during synthesis, resulting in failure of the FPGA implementation. Achieving the same hardware timing optimizations also required very precise modelling techniques to force the synthesis tool to recognize specific design elements such as tri-state buffers.

The Instructional Processor has been successfully translated from its original VHDL to an equivalent Verilog model. By focusing on describing each hardware component, rather than just revising syntax, the design maintained its functional integrity. Simulation results for both models exactly replicate all register transfers and timing for multiple test sequences. The hardware synthesized by the Xilinx tools was also very consistent in both device utilization and maximum clock frequency. The project was a success and the Instructional Processor continues to achieve its goal as a valuable instructional tool, now in two languages.

Hayne, R. J. (2018, June), Translating the Instructional Processor from VHDL to Verilog Paper presented at 2018 ASEE Annual Conference & Exposition , Salt Lake City, Utah. 10.18260/1-2--31160

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