Asee peer logo

Understanding Cpu Pipelining Through Simulation Programming

Download Paper |


2005 Annual Conference


Portland, Oregon

Publication Date

June 12, 2005

Start Date

June 12, 2005

End Date

June 15, 2005



Conference Session

Computers in Education Poster Session

Page Count


Page Numbers

10.1371.1 - 10.1371.9



Permanent URL

Download Count


Request a correction

Paper Authors

author page

Michael Filsinger

Download Paper |

NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Understanding CPU Pipelining Through Simulation Programming Michael D. Filsinger University of Cincinnati


Understanding the operation of modern Central Processing Units (CPUs) is essential for all Computer Engineering Technology students, but the black box nature of the CPU prevents the easy demonstration of many of the features of a modern CPU. In particular, pipelining has a tremendous effect on the real-world performance of a CPU. Typically, benchmarks are used to compare different processors, though the validity of such results is considered highly questionable. Alternatively, a variety of software packages exist for simulating the operation of a CPU. However, I have found in my Computer Architecture class that making the students write their own simple simulator programs results in a better understanding of some of the design issues involved in CPU performance. In this way, students can study the effects of the pipeline without needing to worry about any of the other details.


All students in the Electrical and Computer Engineering Technology programs at the University of Cincinnati take a Junior/Senior level course in Computer Architecture. One of the most important concepts from this class is the effect of pipelining on Central Processing Unit (CPU) performance. This is one of the most fundamental issues facing CPU designers today. Unfortunately, it is difficult to demonstrate the effects through practical experimentation, as one cannot simply compare the performance of a non-pipelined CPU versus a pipelined CPU, since the performance will likely have been strongly affected by other optimizations in the (presumably newer) pipelined CPU.

This paper will examine one project I use to demonstrate this concept. In this project, students write a simulation of a series of “instructions” moving through a CPU data path. This simulation takes three forms: a single-cycle implementation, where each instruction takes exactly one clock cycle to execute (but this clock cycle must be long enough to handle all of the requirements of the longest instruction type); a multi-cycle implementation, where each instruction can take multiple clock cycles, depending on how many subtasks are involved in its execution; and a pipelined implementation, where multiple instructions can simultaneously be in different partial stages of execution. By writing simulations of this process, students can focus on the effects of pipelining on the performance of their simulated system. For the sake of simplicity, we do not actually consider what the instructions are, nor do we take branch or data hazards into consideration.

In later sections, I outline the basic problem of CPU pipelining, the actual programming project assigned to the students, the benefits of this approach, and student feedback. I also present an

Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright © 2005, American Society for Engineering Education

Filsinger, M. (2005, June), Understanding Cpu Pipelining Through Simulation Programming Paper presented at 2005 Annual Conference, Portland, Oregon. 10.18260/1-2--14736

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2005 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015