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Use of a CPLD in an Introductory Logic Circuits Course with Software and Hardware Upgrade

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2014 ASEE Annual Conference & Exposition


Indianapolis, Indiana

Publication Date

June 15, 2014

Start Date

June 15, 2014

End Date

June 18, 2014



Conference Session

Computer Hardware

Tagged Division

Computers in Education

Page Count


Page Numbers

24.1303.1 - 24.1303.16



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Paper Authors


Ying Yu University of Hartford

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Dr. Ying Yu received her B.Eng. from Fudan University, Shanghai, China, in 2000. She received her M.Eng. and Ph.D. in Electrical Engineering from Brown University, R.I., USA, in 2003 and 2007, respectively. Since 2008, she has been teaching at the University of Hartford. Her current research interests are audio and speech signal processing, acoustic scene classification, speaker identification and verification, and teaching with new educational methods, including peer instruction, video games, and state-of-the-art CAD tools.

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Krista M Hill University of Hartford

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Dr. Krista M. Hill is an associate professor in Electrical and Computer Engineering at the University of Hartford in Connecticut. PhD and MSEE from Worcester Polytechnic Inst. in Worcester MA, and previously a project engineer at Digital Equipment Corp. She instructs graduate and undergraduate computer engineering computer courses, directs graduate research, and performs research involving embedded microprocessor based systems. Her current projects involve small system design, signal processing, and intelligent instrumentation.

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Use of a CPLD in an Introductory Logic Circuits Course with Software and Hardware UpgradeAbstractThis paper documents our continued efforts to integrate the use of complex programmable logicdevices (CPLD) into our introductory logic circuits course at [University Name]. Althoughprogrammable logic devices (PLDs) have been long introduced in our advanced courses, thewidespread acceptance demands that PLDs be introduced earlier in the electrical and computerengineering curriculum. In the fall semester of 2011, we selected CPLD as the choice of PLDs tobe used in the introductory logic circuits course, because CPLD allows for an experience thatincludes modern design tools and devices, as well as hands-on activities. Our CPLD moduleallows such a device to be used with a classic breadboard. In prior research we found that usingthis module, students can easily identify the CPLD and with modest wiring they can constructcircuits that they feel are both satisfying and engaging.In this paper, the most recent developments, which include both software and hardwareupgrades, along with student feedback, are documented. With the Xilinx XC9536 CPLDs nowobsolete we adopted a newer CPLD, and designed a new logic circuits trainer. The newerXC9536XL CPLDs require 3.3V signals and power, which is not compatible with anycommercially available trainer that we are aware of. Facing this inevitable trend to lower Voltagelogic, we decided to adopt the 3.3V CPLD devices and design our own trainer that provides 3.3Vpower and I/O signal. The artwork for the module and trainer are available under free softwarelicense, for your use.On the software front, we revised our tutorial and we now have our students working with testbench files. Our CAD software was upgraded from Xilinx ISE Version 10.1 to Version 13.2. Inthe past, we specifically chose Xilinx ISE 10.1 32-bit version for its graphical test benchgenerator which is very convenient for students to use when performing simulation.Unfortunately, this feature is absent in the 64-bit version as well as the subsequent versions ofXilinx ISE, including 13.2. On the other hand, version 13.2 is much more stable and bug-free incomparison to version 10.1. In adopting version 13.2, the biggest concern was how studentswould generate the simulation test bench, which involves modifying VHDL codes, since studentsdo not learn to write hardware description language (HDL) in an introductory logic circuitscourse. ISE provides an aid in generating a skeleton which with our revised tutorial, our studentsare able to modify for their own use.New lecture material was developed to help students understand these upgrades includinghistorical context. New lab content was developed to address some concerns from our previousexperience, which include: a) start-up activities to help students master the CAD software betterand earlier in the course; b) incorporating the use of hierarchical design earlier and in moreexperiments. Students’ experience and feedback, instructors’ observations are presentedconcerning both the hardware and software upgrades along with other changes made. In the end,we present future plans.

Yu, Y., & Hill, K. M. (2014, June), Use of a CPLD in an Introductory Logic Circuits Course with Software and Hardware Upgrade Paper presented at 2014 ASEE Annual Conference & Exposition, Indianapolis, Indiana. 10.18260/1-2--23236

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