Asee peer logo

Use of FPGAs in a Digital System Design Course with Computer Gaming Applications

Download Paper |


2018 ASEE Annual Conference & Exposition


Salt Lake City, Utah

Publication Date

June 23, 2018

Start Date

June 23, 2018

End Date

July 27, 2018

Conference Session

COED: EE Topics

Tagged Division

Computers in Education

Page Count




Permanent URL

Download Count


Request a correction

Paper Authors


Cheng Chih Liu University of Wisconsin-Stout

visit author page

Cheng Liu is an Associate Professor in the Computer and Electrical Engineering Program at University of Wisconsin Stout. He taught courses in computer and electrical engineering program. His teaching and research interests are FPGA based digital systems, microprocessor system design, and embedded systems.

visit author page

Download Paper |


This article discusses our continuing efforts to integrate the Field Programmable Gate Arrays (FPGAs) into the digital system design course. The course follows on from the first-year digital logic course. Programmable gate arrays had previously been introduced in our senior-level embedded system course, but the recent trend toward applications in industry demanded that FPGAs be introduced earlier in the Electrical and Computer Engineering curricula. In the fall semester of 2009 we began introducing FPGAs into the digital system design course. This allowed our second-year students to explore high-level circuit designs with a state-of-the-art Computer-Aid Design suite (CAD) with Xilinx’s FPGAs.

In this work, we describe the revision for the digital system design course starting in 2015, including software and hardware upgrades that improved our hands-on laboratory exercises. Because Xilinx ISE 14.7 version no longer supported newer FPGAs devices, we adopted the Xilinx Artix-7 FPGAs on the Basys-3 educational board and the Xilinx Vivado design suite.

We also provide some historical context regarding to the evolution of the laboratory exercises used for this course. Two new lab exercises were developed to address student concerns from the student survey in 2015, including introducing the hierarchical design flow for FPGAs earlier in the course, as well as lack of real-world examples in the lab exercises. In this paper, we describe two new computer gaming labs added in 2016 along with evaluation data showing marked improvement in students’ perception of the course.

Liu, C. C. (2018, June), Use of FPGAs in a Digital System Design Course with Computer Gaming Applications Paper presented at 2018 ASEE Annual Conference & Exposition , Salt Lake City, Utah. 10.18260/1-2--31188

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2018 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015