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Verification Of Hardware Description Language Designs

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Conference

2006 Annual Conference & Exposition

Location

Chicago, Illinois

Publication Date

June 18, 2006

Start Date

June 18, 2006

End Date

June 21, 2006

ISSN

2153-5965

Conference Session

Digital System Design

Tagged Division

Electrical and Computer

Page Count

12

Page Numbers

11.1425.1 - 11.1425.12

Permanent URL

https://peer.asee.org/308

Download Count

36

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Paper Authors

biography

Joanne DeGroat Ohio State University

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Dr. Joanne DeGroat is an Associate Professor at The Ohio State University in the Department of Electrical and Computer Engineering. She received her BS degree in Engineering Science from Penn State University, her MSEE from Syracuse University, and her Ph.D. in Electrical and Computer Engineering from the University of Illinois. Her research interests are in computer architecture, VLSI, mixed signal VLSI, hardware description languages (HDLs), and verfication of HDL designs. Recently she has been conducting research in the areas of HDL verification, FPGA architectures, and RF VLSI design.

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Verification of Hardware Description Language Designs Joanne E. DeGroat Department of Electrical and Computer Engineering The Ohio State University Abstract:

The field of HDL verification is relatively new and addresses the need to verify that the HDL model does indeed implement what has been specified. This is especially important as almost all digital integrated circuits are synthesized from HDL descriptions. This paper outlines the content of the course Verification of Hardware Description Language (HDL) Models at Ohio State University. This course currently consists of lectures and four verification projects. This paper discusses the course and the four projects.

I. Overview

The design of modern digital integrated circuits has changed dramatically in the last 15 years. Technology has advanced to the point to where we are able to reliably produce chips with millions of logic gates on a single integrated circuit die. This translates into very significant logic function for a single chip. The only way that design of chips capable of effectively using this much functionality is possible is with advanced tools and design methodology. Part of the methodology is a rigorous partitioning and structuring of the design. One has only to look at a photomicrograph (photo of the circuitry on an IC) of a chip from the early or mid 1970s to the photomicrograph of a modern processor to see this. The early chips looked like a bowl of spaghetti. Modern chip are well organized and are a structure of interconnected blocks.

This is well supported by the current design methodology that involves the use of Hardware Description Languages (HDLs) for the design of the IC. Modern HDLs are hierarchical and support the partitioning of the design into logical functioning blocks. The use of HDLs in design has allowed more significant verification of the design before it is first fabricated. In the early 1990s the focus was on getting a chip that fabricated and functioned. With the advent of HDL synthesis, getting functioning first run chips was no longer an issue. The emphasis quickly evolved into to not only producing a chip that functioned, but that functioned as desired in the environment for which it was being designed. This has given rise to the field of HDL Verification. And this field has grown rapidly. It has reached the point where numerous corporations not only have design engineers but also now have an equal number of verification engineers.

This paper will highlight the course content of “Verification of Hardware Description Language (HDL) Models” at The Ohio State University. The course was first offered in SPRING 2001 and was one of the first HDL Verification courses taught anyplace. It is the second course in the HDL sequence. The first course covers modeling with a Hardware Description Language at various levels of abstraction. It starts with modeling at the data flow level with a one-to-one correspondence of HDL statement to

DeGroat, J. (2006, June), Verification Of Hardware Description Language Designs Paper presented at 2006 Annual Conference & Exposition, Chicago, Illinois. https://peer.asee.org/308

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