Asee peer logo

Vhdl And Small Format Color Displays

Download Paper |

Conference

2005 Annual Conference

Location

Portland, Oregon

Publication Date

June 12, 2005

Start Date

June 12, 2005

End Date

June 15, 2005

ISSN

2153-5965

Conference Session

Curriculum Development in Computer ET

Page Count

11

Page Numbers

10.1446.1 - 10.1446.11

Permanent URL

https://peer.asee.org/15238

Download Count

65

Request a correction

Paper Authors

author page

Jeffrey Lillie

Download Paper |

Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 2548 VHDL and Small Format Color Displays ”Video Images Make Learning Fun” Jeffrey S. Lillie

Abstract

Rochester Institute of Technology requires a course in Principals of Design Automation for Electrical Engineering Technology and Computer Engineering Technology students. At the completion of the course, students are expected to know the basics of coding for synthesis, test bench techniques, modelsim simulator, and the Xilinx tool flow for targeting complex programmable logic devices (CPLD’s) and field programmable gate arrays (FPGA’s).

A quick survey of the typical college student showed that they love video images. It could be a video clip captured with a digital camera, a digital video playing on their laptop, or digital images captured with their camera phone. This paper reviews and discusses how an FPGA platform was selected and integrated with a QVGA(320x240) color display. It details how an eight lab sequence was developed to allow the students to accomplish a project goal of playing a video image sequence on the QVGA display. This paper also illustrates how additional ABET outcomes such as applied technical problem solving, technical writing, configuration management, team dynamics, communications, and ethics were integrated into the course content.

Introduction Rochester Institute of Technology requires a course in Principals of Design Automation for Electrical Engineering Technology and Computer Engineering Technology students. At the completion of the course, students are expected to know the basics of coding for synthesis, test bench techniques, modelsim simulator, and the Xilinx tool flow for targeting complex programmable logic devices (CPLD’s) and field programmable gate arrays (FPGA’s). The prerequisites are Digital System Design and a formal, structured programming course.

Course Description An advanced course in the VHSIC Hardware Descriptive Language (VHDL). The course provides an in-depth coverage of the language and describes the VHDL design environments that will be used for synthesis and verification. Topics include the behavioral, dataflow, and structural modeling of both combinatorial and sequential logic, design methodologies, synthesis and optimization. An IEEE-1076 standard VHDL development system will be extensively utilized to synthesis VHDL for PLD, CPLD and FPGA applications. The prerequisites are Digital System Design and a formal, structured programming course. Class 3, Lab 2, Credit

Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition 1 Copyright © 2005, American Society for Engineering Education

Lillie, J. (2005, June), Vhdl And Small Format Color Displays Paper presented at 2005 Annual Conference, Portland, Oregon. https://peer.asee.org/15238

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2005 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015