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Vhdl Modeling And Synthesis In The Laboratory

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Conference

1999 Annual Conference

Location

Charlotte, North Carolina

Publication Date

June 20, 1999

Start Date

June 20, 1999

End Date

June 23, 1999

ISSN

2153-5965

Page Count

12

Page Numbers

4.589.1 - 4.589.12

Permanent URL

https://peer.asee.org/8042

Download Count

99

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Paper Authors

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Raji Sundarajaran

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Christina Sisterna

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Charles A. Lipari

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Robert W. Nowlin

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 2647

VHDL Modeling and Synthesis in the Laboratory

Charles. A. Lipari, Cristian Sisterna, Raji Sundarajaran and Robert W. Nowlin Arizona State University-East

ABSTRACT

New industry digital design automation tools available at the Department of Electronics and Computer Engineering Technology of Arizona State University-East require special attention as to the methods and practices required to develop real-world applications. Realization in the laboratory specifies and amplifies this knowledge to the student of digital systems design. The aim of this paper is to detail all the necessary steps to realize laboratory applications using industry level VHDL tools and rapid prototyping hardware. Presented in this paper are typical illustrations of the synthesis of VHDL for commonly encountered circuits. Behavioral, rather than gate-level, models are used to target particular synthesis structures, i.e. flip-flops, multiplexors, counters, and state machines. The design is integrated into a modular hierarchy that allow reusability in larger systems. Timing test sets are used at each level of expression leading to implementation. The APS X84 Xilinx FPGA board is used to implement the design for functional verification, testing, and making measurements at speed.

I. Introduction

VHDL6,7 is but one example of a Hardware Description Language (HDL) used in industry. It can be used for modeling other things besides digital systems, however, the usefulness of VHDL for digital design is to write instructions that can be executed in realizable parallel hardware, something very different from conventional coding in languages like C or C++. The alternative to an HDL is schematic entry. Schematics are still popular for low-level digital design, since they give a view of component and component block connectivity directly mapable to the logic circuit devices and connections, respectively. VHDL has several advantages over schematics, but requires a different approach to be useful. VHDL coding either describes connections and low-level gate functions (structural VHDL) or functional behavior (behavioral VHDL). Schematics give strictly structural descriptions using instances of components from a given library. To describe a circuit in VHDL, instead of exactly reproducable components, implies that only synthesizable constructs of VHDL be used8. The code is compiled to the target device library for the given technology, i.e. binds the code to instances of the given technology library. The higher the level of description, the more technology independent and reusable is the design. The key to reusability is to make HDL structural or behavioral descriptions that are realizable from many component libraries. Industry’s approach to this is to embed reusable core designs by relinking them into a complex systems-on-a-chip, realized as Application Specific Integrated Circuit (ASIC).

Sundarajaran, R., & Sisterna, C., & Lipari, C. A., & Nowlin, R. W. (1999, June), Vhdl Modeling And Synthesis In The Laboratory Paper presented at 1999 Annual Conference, Charlotte, North Carolina. https://peer.asee.org/8042

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