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Vhdl Projects To Reinforce Computer Architecture Classroom Instruction

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Conference

2007 Annual Conference & Exposition

Location

Honolulu, Hawaii

Publication Date

June 24, 2007

Start Date

June 24, 2007

End Date

June 27, 2007

ISSN

2153-5965

Conference Session

Issues in Computer Education-HDL

Tagged Division

Computers in Education

Page Count

16

Page Numbers

12.1588.1 - 12.1588.16

DOI

10.18260/1-2--1676

Permanent URL

https://peer.asee.org/1676

Download Count

908

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Paper Authors

biography

Ronald Hayne The Citadel

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Ronald J. Hayne, PhD, is an Assistant Professor in the Department of Electrical and Computer Engineering at The Citadel. His professional areas of interest are digital systems and hardware description languages. He is a retired Army officer with experience in academics and Defense laboratories.

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

VHDL Projects to Reinforce Computer Architecture Classroom Instruction

Abstract

Exploration of various computer architecture constructs needs reinforcement beyond pencil and paper homework problems. Unfortunately, laboratory exercises based on microprocessor trainers are limited to a single architecture and a resolution of single assembly language instructions. A hardware description language, such as VHDL, can be used to provide simulation-based application of the classroom instruction regardless of the course text. Models of computer components such as registers, memory, and ALUs can be readily defined to match textbook examples and then combined to demonstrate multiple architectural concepts. Students with basic knowledge of VHDL from their prerequisite digital logic course are able to modify and use these models to simulate computer behavior at the register transfer level with data and control signal visibility at each clock cycle.

A program of instruction has been developed that uses VHDL homework exercises and a capstone design project to provide hands-on application of course concepts using modern design tools. Exercises include addressing modes, microprogrammed control, and computer arithmetic. The design project models a multi-bus architecture and hardwired control unit from the text to implement a basic instruction set. An example assembly language program can be loaded into memory and executed in simulation on the model computer. Results are verified by monitoring control signals, buses, and registers, as well as final dumps of memory and register contents.

Student feedback has been very positive that the VHDL exercises provided reinforcement of classroom concepts and allowed them to visualize results via simulation. Over two-thirds of the students were able to implement a completely functional design project computer model which successfully executed the test program. The methodology was to combine/modify instructor provided VHDL models, rather than turning the course into a “programming” class. This kept the focus on “hardware description” and did not rely on coverage of the language by the course text. The resulting combination of textbook and classroom instruction with VHDL modeling and simulation exercises provided students with a more robust learning experience and exposure to state-of-the-art design tools.

Introduction

Teaching computer architecture effectively requires reinforcement beyond pencil and paper homework problems. Some form of hands-on laboratory exercises are desirable to provide practical observation of the classroom constructs. Microprocessor trainers are one option, but unless investment is made in multiple systems, exercises are limited to a single architecture. With a resolution of single assembly language instructions, the focus often shifts to assembly language programming of the target architecture, rather than allowing exploration of various computer architecture concepts.

Hayne, R. (2007, June), Vhdl Projects To Reinforce Computer Architecture Classroom Instruction Paper presented at 2007 Annual Conference & Exposition, Honolulu, Hawaii. 10.18260/1-2--1676

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