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Work in Progress - Teaching Hardware Implementation of Digital Signal Processing Algorithms on FPGAs

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2012 ASEE Annual Conference & Exposition


San Antonio, Texas

Publication Date

June 10, 2012

Start Date

June 10, 2012

End Date

June 13, 2012



Conference Session

Computers in Education Division Poster Session

Tagged Division

Computers in Education

Page Count


Page Numbers

25.1486.1 - 25.1486.6



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Paper Authors


Nader Rafla Boise State University

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Dr. Nader Rafla, P.E., received his M.S.E.E. and Ph.D. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1984 and 1991 respectively. His Doctoral research concentrated on object recognition and localization from range image data, force-torque, and touch sensors data.

From 1991 to 1996, he was an Associate Professor in the department of Manufacturing Engineering at the Central State University. Where he taught courses related to the electrical engineering component of the program. In the mean time, he developed and was involved in a research program in applied image processing.

In January, 1997, He joined the newly developed electrical and computer engineering program at Boise State University where he is currently an Associate professor and chair of the Electrical Engineering Department. He led the development and starting of the M.S. of Computer Engineering; He taught several courses and supervised numerous M.S. thesis and Senior Design Projects. He also has conducted research and consulted in R&D for Micron Technology, Hewlett Packard and others.

Dr. Rafla’s area of expertise is systems on a programmable chip and embedded & microprocessor-based system design; Neuromorphic systems; and implementation and hardware architectures of digital image and signal processing algorithms applied to recognition, identification, inspection, automation and control. He is a senior member of the IEEE organization and several societies and a member of the ASEE organization.

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Teaching Hardware Implementation of Digital Signal Processing Algorithms on FPGAsAbstractIn today’s world the amount of sampled data is increasing as more efficient and faster analog todigital converters are becoming available. There is a need to implement signal processingsolutions on hardware to accommodate the current processing rates of this data. FPGAs are apopular choice in academia and industry research because hardware solutions can be prototyped,implemented, and tested on FPGAs with ease. In this paper we present the outline and structureof a new graduate level course titled “Hardware Implementation of Digital Signal Processing”,offered at ----- ----- University as part of the Master of Science program in ComputerEngineering. The prerequisites of this course include background in digital hardware designusing any Hardware Description Language (VHDL or Verilog) and a working knowledge ofdiscrete-time or digital signal processing theory. This new course starts by reviewing conceptsfrom both prerequisites, and then introduces the entire design process for DSP algorithms fromspecifications and simulation to implementation and verification. Furthermore, the courseexposes students to advanced concepts in hardware design (e.g. floating point arithmetic andCORDIC) and digital signal processing (e.g. FIR, IIR, and adaptive filters). The primaryemphasis is on the implementation cost tradeoffs and timing issues involved in designingcompact, efficient, and low-power hardware solutions for DSP algorithms. MATLAB is used forstudying and understanding the DSP algorithms, Simulink with the Xilinx suite of tools fordesign and synthesis of the hardware solutions into FPGAs, and QuestaSim for functionsimulation and design verification. This course has a project-based hands-on format wherestudents individually design, test and verify, and implement into an FPGA a series of smallprojects. Each project covers in detail all aspects of the implementation of a particular DSPconcept (e.g. basic arithmetic operations, FFT, FIR and IIR filters, etc.). These projects thenclimax into a major final project that requires the research, hardware design, simulation, andimplementation of an advance DSP system.

Rafla, N. (2012, June), Work in Progress - Teaching Hardware Implementation of Digital Signal Processing Algorithms on FPGAs Paper presented at 2012 ASEE Annual Conference & Exposition, San Antonio, Texas. 10.18260/1-2--22243

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