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Teaching Digital Logic Design Using CAD Tools in a Teaching-Oriented University

Guoping Wang

Department of Engineering, Indiana University Purdue University Fort Wayne

Abstract

Digital Logic System Design is a very important course in electrical and computer engineering programs. Current teaching methods propose the integration of Hardware Description Language (Verilog or VHDL). This paper describes the author’s experience in integrating Xilinx ISE tools and FPGA/CPLD logic devices into the teaching of digital logic system in a teaching-oriented university. The author’s experience indicates that integrating CAD and FPGA/CPLD instead of the early introduction of HDL can better facilitate the learning of digital system design.

Index term: -- Engineering courses, logic design, digital system design, VHDL

Introduction

Digital hardware plays a dominant role in many electrical and computer engineering products today. The introductory course Digital System Design is a core requirement course for electrical and computer engineering students. Integrating HDL (Hardware Description Language), such as Verilog or VHDL into the teaching of logic system design has been proposed in the past 1-5. However, in the early introduction of HDL, the instructor has to focus on explaining the important differences between HDL and other computer programming languages that students are familiar with. Students may focus upon the complex features of HDL instead of the fundamentals and principles of logic systems. If HDL is introduced at the same time as the logic system, then it is a big distraction from the teaching of these fundamental principles and practices of digital logic systems. These basic principles include Boolean algebra, Karnaugh maps, synchronous and asynchronous sequential circuits, to name a few. Because the schematic concepts and the digital logic blocks are the blueprints of digital logic systems, thus it is very necessary to help students learn the basic principles first instead of jumping to VHDL directly. While it is agreed that students must learn about these digital logic functions and their implementations, whether to introduce HDL language too early into the teaching of digital system designs remains a controversy. The author’s experience at IPFW (Indiana University Purdue University – Fort Wayne) shows that the schematic design using CAD tools and FPGA/CPLD implementation in the lab sessions rather than HDL can be introduced to students early on to facilitate their learning of digital logic systems.

IPFW is a regional teaching university that serves northeast Indiana. It is affiliated with both Indiana University and Purdue University. Most students are non-traditional students from

Proceedings of the 2005 American Society for Engineering Education Annual Conference & Exposition Copyright ©2005, American Society for Engineering Education

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Wang, G. (2005, June), Teaching Digital Design Using Cad Tools In A Teaching Oriented University Paper presented at 2005 Annual Conference, Portland, Oregon. 10.18260/1-2--14224