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On the Use of a Soft Processor Core in Computer Engineering Education Abstract

The microprocessor course at most universities has traditionally been taught using a discrete microprocessor such as the Motorola 6800 series, Intel x86 series, or IBM PowerPC series. With the continued increase of usable field-programmable gate arrays (FPGA) gates and improvement of off-the- shelf soft processor core computer-aided design (CAD) tools, this practice is beginning to change. It is now possible to teach a microprocessor course using a soft processor core such as Xilinx Microblaze or Altera Nios. Such tools provide the user a graphical user interface to configure a 32-bit processor with the desired peripherals. This type of tool provides flexibility that was previously non existent.

In the traditional method, interface devices need to be built into the microprocessor prototyping printed- circuit board. Otherwise, the additional interface devices will need to be built and wired to the main board. With the use of a soft processor core and an FPGA board with a sizable FPGA, all of the required interface logic can be built into the FPGA. Such hardware logic can be described using hardware description languages (Verilog or VHDL) or schematic capture. The FPGA functionality can be changed easily by downloading a new bit file (or configuration file) to the FPGA after re-running the synthesis tools.

These off-the-shelf tools have also been packaged with software development tools such as compilers, debuggers, and instruction set simulators, which are usually GCC-based. The encapsulation of hardware and software components into one FPGA design process also allows the hardware and software designs to be simulated – together – using a hardware description language simulator. However, the use of such tools doesn’t come free (remember, there is no such thing as a free lunch!). There are many pitfalls when using a soft processor core in teaching. These off-the-shelf CAD tools usually have steep learning curves. In some cases, a non-working design can have problems in the hardware or software portion, which can be difficult to track. This paper describes teaching microprocessor design using a soft processor core, our experiences, our methodology, and the pitfalls in depth.

1 Introduction During the last three decades, the microprocessor course has traditionally been taught using a discrete microprocessor such as the Motorola 6800 series, Intel x86 series, or IBM PowerPC series. The usual topics include the architecture of a selected microprocessor or microcontroller, assembly and C programming, and devices interfacing. Usually, an off-the-shelf prototyping board with the desired microprocessor/microcontroller is used in the laboratory to introduce the hands-on experience. This well- thought-out course structure has been working really well, and students completing this course usually have the skills to build a small-scale system.

Things are starting to change in embedded system design due to field programmable devices. In the old days, programmable devices were used as glue logic, but their use is no longer limited to this role. Programmable devices have also been benefited from the shrinking of transistors, allowing more resources to be packed into a programmable device. With the continued increase of usable FPGA gates and improvement of off-the-shelf soft processor core computer-aided design (CAD) tools, it is now possible to teach a microprocessor course using a soft processor core such as Xilinx Microblaze [1] or Altera Nios [2]. Such tools provide the user a graphical user interface to configure a 32-bit processor with the desired peripherals. This type of tool provides flexibility that was previously non existent.

In order to use the processor effectively and the FPGA efficiently, vendors package a suite of tools with software development tools such as compilers, debuggers, and instruction set simulators, which are

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Loo, S. M. (2006, June), On The Use Of A Soft Processor Core In Computer Engineering Education Paper presented at 2006 Annual Conference & Exposition, Chicago, Illinois. 10.18260/1-2--165