Rafla, N. (2011, June), Teaching Digital Systems Verification Methodologies using SystemVerilog  Paper presented at 2011 ASEE Annual Conference & Exposition, Vancouver, BC. 10.18260/1-2--18558

\bibitem{asee_peer_18558}
  Rafla, N. (2011, June), \emph{Teaching Digital Systems Verification Methodologies using SystemVerilog}
  Paper presented at 2011 ASEE Annual Conference \& Exposition, Vancouver, BC.
  10.18260/1-2--18558

Nader Rafla.  "Teaching Digital Systems Verification Methodologies using SystemVerilog".  2011 ASEE Annual Conference & Exposition, Vancouver, BC, 2011, June.  ASEE Conferences, 2011.  https://peer.asee.org/18558 Internet.  24 Apr, 2024

\bibitem{asee_peer_18558}
  Nader Rafla.
  "Teaching Digital Systems Verification Methodologies using SystemVerilog".
  \emph{2011 ASEE Annual Conference \& Exposition, Vancouver, BC, 2011, June}.
  ASEE Conferences, 2011.
  https://peer.asee.org/18558 Internet.  24 Apr, 2024

@INPROCEEDINGS{asee_peer_18558
author = "Nader Rafla"
title = "Teaching Digital Systems Verification Methodologies using SystemVerilog"
booktitle = "2011 ASEE Annual Conference \& Exposition"
year = "2011"
month = "June"
address = "Vancouver, BC"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/18558}
number = {10.18260/1-2--18558}
}

TY  - CPAPER
AB  - Teaching Digital Systems Verification Methodologies using SystemVerilogWith the growing complexity of modern digital system and embedded system designs,the task of verification has become the key to achieving the faster time-to-marketrequirement for such designs. This paper describes a graduate level course, offered atBoise State University as a part of the Masters of Science program in ComputerEngineering, in Verification of Digital System designs using SystemVerilog. This coursedoes not only teach syntax and semantics but also a coverage-driven, constrained random,and assertion based verification methodologies employing the advanced features ofSystemVerilog to ensure that the designs meet given design specifications. The coursealso emphasizes the practical aspects of verifications through providing the studentshands-on experience on commercial verification tools such as QuestaSim AdvancedFunctional Verification from Mentor Graphic's Advanced Verification Environment. The short-term and long-term goals of the course are explained along with the course content andformat. The course is designed around small projects to illustrate the main concepts,tools, and language usage. A mid-term and a final project are also offered that require anautomated verification environment to be designed and tested.
AU  - Nader Rafla
CY  - Vancouver, BC
DA  - 2011/06/26
PB  - ASEE Conferences
TI  - Teaching Digital Systems Verification Methodologies using SystemVerilog
UR  - https://peer.asee.org/18558
DO  - 10.18260/1-2--18558
ER  -