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Active-HDL, Multisim, Cadence… There has got to be a better way to teach CAD/E Tools Abstract

Numerous computer aided design (CAD) and engineering (CAE) software products exist to automate the design process, but how does an instructor efficiently incorporate those tools into the classroom to facilitate learning? A typical electrical engineering major at this school may use up to twenty different software products over the course of two and a half years. CAD/E tools play an important role in enabling students to take concepts learned in the classroom and apply them to real world problems and significantly enhances student learning. Many text books come with support for a specific CAD/E tool with many examples, but gloss over the use of the CAD/E application and expect that the student already knows the software or will learn it on their own. Many courses do the same, based on the amount of material they are required to cover, and there is not enough time to also instruct students on the operation of a specific CAD/E tool. In our digital logic and computer architecture courses, we currently spend approximately two hours over two semesters teaching students to use Active-HDL; we require students to use the program in multiple labs and homework assignments to reinforce key concepts in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Due to the fact that our instruction only touches the surface of the program’s capabilities, students expend a significant amount of additional time and effort learning to use Active-HDL at the expense of learning the key concepts we would like to emphasize with VHDL. Too often the students spend countless hours attempting to learn the software and fail to grasp the actual concepts that the software was supposed to reinforce. One course of action to eliminate this problem is to stream line the software tools used throughout the curriculum. This would require a conscious, program-wide effort to redesign the course curriculum using only one CAD/E product and is not a feasible solution to our problem. Instead, we propose a coordinated software effort within a program and an assessment program geared specifically towards the CAD/E tools used in each course to help instructors enhance classroom instruction and out-of-class independent student learning of new CAD/E Software. This paper will focus on the software application Active-HDL, the programming language VHDL, and an assessment tool we use to improve student proficiency with these CAD/E tools.

Background

The original objective of our current research was to develop a set of tools we could apply to help students learn the software program Active-HDL and the programming language VHDL. Our intent was to develop these tools within the digital logic thread of our Electrical Engineering program, and then apply these tools to other software applications and programming languages within other threads of our EE program. We believed that we could develop innovative techniques to facilitate improved learning.

In our Master Teacher Program, instructors learn about student learning techniques, course analysis and course design.1 One of the requirements is to complete a classroom assessment research project. As we looked at course assessment in our digital logic and computer architecture courses, we identified issues with students spending an inordinate amount

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Gribschaw, J., & Patterson, P., & Goda, B. (2007, June), Active Hdl, Multisim, Cadence... There Has Got To Be A Better Way To Teach Cad/E Tools Paper presented at 2007 Annual Conference & Exposition, Honolulu, Hawaii. 10.18260/1-2--2451