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A Simulated Mano Machine An Novel Project For Computer Architecture Class

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Conference

2008 Annual Conference & Exposition

Location

Pittsburgh, Pennsylvania

Publication Date

June 22, 2008

Start Date

June 22, 2008

End Date

June 25, 2008

ISSN

2153-5965

Conference Session

ECE Poster Session

Tagged Division

Electrical and Computer

Page Count

28

Page Numbers

13.103.1 - 13.103.28

DOI

10.18260/1-2--3110

Permanent URL

https://peer.asee.org/3110

Download Count

7211

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Paper Authors

biography

Vicky Fang Cedarville University

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assistant professor

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biography

Clinton Kohl Cedarville University

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associate professor

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

A Simulated MANO Machine -- A Novel Project for Undergraduate Computer Architecture Class Abstract:

Hands-on experience and visualization are both crucial to enhance undergraduate engineering education. This paper will describe a novel project that we feel meets both of these key elements for a first undergraduate computer architecture class. Instruction level simulation, though helpful, does not expose students to the hardware behavior or the internal instruction behavior. Likewise, FPGA simulation alone will not provide a good real-time visualization of the many digital signals which make up the microprocessor hardware. To avoid such drawbacks, we designed a project that requires each student to implement a 16-bit general-purpose computer on a real time digital logic simulator named Cedarlogic.

Students are given an instruction set specified in the textbook and a short assembly level test program. Students will: 1) build the entire computer hardware using the Cedarlogic simulator from fundamental logic gates; 2) write an assembler to translate the test program into binary code; 3) load the program into the memory of their computers; and 4) run the test program on their hardware. Cedarlogic is a unique real-time digital logic simulator designed by six of our senior engineering and computer science students for their capstone project over two successive years. In Cedarlogic, a logic high signal is shown in red, a logic low signal is shown in black, while high impedance is shown in green. As a result, when a project is working correctly students can actually watch all the internal signals within the computer “dancing” with the clock. Students can watch how the address buses change, how the data is latched, and how the ALU calculates... It is a real-time simulation, an experience which uncovers the mysterious veil of the computer. The students are excited to watch their computer executing the test program, clock cycle by clock cycle. It is truly an enlightening experience for the undergraduate computer architecture student.

Introduction

Computer Architecture is a fundamental course in every computer engineering curriculum. Two important goals of the computer architecture class are to give the students a good understanding of: 1. how digital hardware is used in the construction of a computer, and; 2. how each instruction propagates through the microprocessor. These goals are especially important for the first exposure of the undergraduate student to computer architecture. Without a good understanding of these basics, all the student will receive will be some vague terminologies and theories. As a result, it will be hard for them to further develop and to receive advanced topics in computer architecture and apply them to the real world.

To fulfill the above goals, many schools have developed projects to give their students hands on practice in these areas. These projects have a variety of forms. One approach is to use computer instruction simulators. For instance, the SPIM simulator will read and execute assembly language programs written for MIPS machines; the emu86 will run x86 instructions. Projects

Fang, V., & Kohl, C. (2008, June), A Simulated Mano Machine An Novel Project For Computer Architecture Class Paper presented at 2008 Annual Conference & Exposition, Pittsburgh, Pennsylvania. 10.18260/1-2--3110

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