Asee peer logo

Abc's Of Processor Design: Introductory Computer Architecture Using The Lis 4

Download Paper |

Conference

1997 Annual Conference

Location

Milwaukee, Wisconsin

Publication Date

June 15, 1997

Start Date

June 15, 1997

End Date

June 18, 1997

ISSN

2153-5965

Page Count

13

Page Numbers

2.51.1 - 2.51.13

DOI

10.18260/1-2--6407

Permanent URL

https://Peer.asee.org/6407

Download Count

349

Request a correction

Paper Authors

author page

Ravi Pendse

author page

Everett L. Johnson

Download Paper |

Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 2520

ABCs OF PROCESSOR DESIGN: INTRODUCTORY COMPUTER ARCHITECTURE USING THE LIS-4

Everett L. Johnson, Ravi Pendse ASEE/Wichita State University

ABSTRACT At Wichita State University a three course sequence in the Digital Design area is offered. First year students are encouraged to take the first course. By their third semester it is possible for a student to enroll in the third course in the sequence. The third course entitled, Introduction to Computer Architecture, introduces the student to the art of designing a processor from scratch. This paper presents the design process and the application of the knowledge obtained in the first two courses in the sequence. The CAD tools used will be discussed as part of the bottom-up design process. Each module of the processor is designed and then integrated into the system as a ASIC cell. CAD tools are used to carry out simulation to verify the design process. The end result is a processor that can run a simple program making use of the CAD simulation tools. Extensions of the original design as special projects are presented.

INTRODUCTION Sometimes it is difficult to see the forest for the trees. The same type of vision obstruction occurs if computer architecture design is presented using a complex instruction set as the design model. Basic design steps are overwhelmed by the necessity to know the instruction set and perform the book keeping required to keep track of all the control and timing signals. At Wichita State University we developed and began using the LIS-4 (4-bit limited instruction set) architecture 15 years ago for use in an Introduction to Computer Architecture course. In 1987 this architecture was presented in a book on digital design [1]. This course is the third in a sequence of 3 undergraduate digital design courses The last 4 years we have made use of a computer aided logic design program called B2LOGIC which allows the students to build, test, and program the computer [2]. In the following sections we give an overview of the LIS-4 and the design as required by the students.

BASIC LIS-4 ARCHITECTURE Registers

Figure 1 shows the basic architecture of the LIS-4. The architecture is a two bus architecture. The two buses are the output bus (BO) and the input bus (BI). The registers and their functions

Pendse, R., & Johnson, E. L. (1997, June), Abc's Of Processor Design: Introductory Computer Architecture Using The Lis 4 Paper presented at 1997 Annual Conference, Milwaukee, Wisconsin. 10.18260/1-2--6407

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 1997 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015