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Session 3532

Using HDLs in an Introduction to Digital Electronics Course Dr. Richard Spillman Pacific Lutheran University

ABSTRACT

The gap between digital electronics as taught in the academic world and digital electronics as it is practiced in industry has widened in the last few years. One aspect of that gap is the use of HDLs in industry. While HDLs are growing in their use in industry, few courses in digital electronics systematically teach students how to design with HDLs. This paper reports on the use of both Verilog and VHDL as a central feature of the digital electronics course at Pacific Lutheran University. Both languages have been taught at different times over the last few years. Initially, Verilog was selected over VHDL because of its close connection to C, which many of the students have used in other classes and because of the close connection between schematics and low level Verilog code. Now, the course is moving towards increasing use of VHDL. The paper outlines the need for HDLs in the introductory digital electronics course and explores the advantages and disadvantages of both Verilog and VHDL. The paper also reports on the the approach used to introduce HDLs to the students and the development of projects requiring HDLs. The results both in terms of student success in the class and reports from students who have graduated are summarized.

Introduction

Hardware Description Languages, HDLs, have emerged as a common tool to aid in the design of digital circuits. Initially, they were used for both simulation and documentation. Now they are also used for synthesis as well. There are a variety of HDLs but two now compete as industrial standards: Verilog and VHDL. While industry makes use of these HDLs, it is still the case that many engineering students are not exposed to either language at all and others only see them during the last stages of their education. At Pacific Lutheran University, both Verilog and VHDL have been used in the first course on digital electronics. Upper division courses assume an initial exposure to an HDL which allows these courses to explore simulation and synthesis in greater detail. This short paper discusses the advantages and disadvantages of the two HDLs and reports on their use in the beginning digital electronics course at PLU.

Using an HDL

Both Verilog and VHDL have been used in the first digitial electronics course, Engr 346, taught at PLU. This course is required by all electrical and computer engineering students and all computer science students. It is usually taken in the second or third year of a students program, though sometimes advanced freshman elect to take the class early. Some computer science students put it off until their senior year. As a result, the class consists of a mix of majors at different stages in their program. For most students it is their first true design course.

Over the last eight years, an HDL has been part of the course content. For the first 6 years the HDL was Verilog and for the last two years it has been VHDL. Regardless of the specific language, the nature of the assignments remained the same. HDLs were introduced by the fourth lecture of the semester long course, just after the basic steps for combinational design were covered. At this point students knew how to design a simple circuit using logic gates so the HDL was introduced as a method of describing the circuit which allows for easy simulation. In this way, the structural modes of either Verilog or VHDL become part of the learning process. From the very beginning of their education students design circuits using both schematics

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Spillman, R. (1998, June), Using Hd Ls In An Introduction To Digital Electronics Course Paper presented at 1998 Annual Conference, Seattle, Washington. 10.18260/1-2--7506