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A Class Project For Low Power Cache Memory Architecture

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Conference

2006 Annual Conference & Exposition

Location

Chicago, Illinois

Publication Date

June 18, 2006

Start Date

June 18, 2006

End Date

June 21, 2006

ISSN

2153-5965

Conference Session

Embedded Computing

Tagged Division

Computers in Education

Page Count

12

Page Numbers

11.14.1 - 11.14.12

Permanent URL

https://peer.asee.org/6

Download Count

1300

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Paper Authors

author page

Yul Chu Mississippi State University

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

A Class Project for Low-Power Cache Memory Architecture

Abstract

This paper presents a class project for a graduate-level computer architecture course. The goal of the project is to let students (two or three students per team) understand the concept of computer hardware and how to design a simple low-power cache memory for future processors. The project consists of three different tasks: 1) Design - Designing a low-power cache memory (instruction or data) at the abstract level after literature research; 2) Code - Writing a simulation program on top of a simulator (e.g., Simplescalar); and 3) Test - Running a test program to evaluate the low-power cache memory by using performance metrics, such as power consumption, cache miss rate, execution time, etc. For the first task, students are required to design their own low-power cache memory. For the second task, they need to write (or modify) a simulation program to implement their design. Finally, they should run benchmark programs through the program to evaluate their cache memory.

1. Introduction

A simulation program has been an important tool to verify the functions for logically designed computer hardware before chip fabrication [1]. A graduate-level computer architecture course, in general, deals with designing a low-power cache memory, branch predictor, superscalar, VLIW, or multi-processors at the abstract level instead of the circuit level [2][3]. After the logical design, students are required to simulate the design with the benchmark programs to inspect whether or not it works properly. This paper presents in detail how to design a low-power cache memory for a graduate-level computer architecture course. Simulation programs are useful for many computer-engineering courses since they can help students to develop and evaluate their ideas with less hardware costs [4][5]. However, some detailed simulators used to discourage students with many options for selection and lengthy lines of code [6]; students can just repetitively implement the fixed, limited operations of the simulators; therefore, it makes difficult for the students to design a new function logic. To implement a low-power cache memory, students are required to design a mapping function, replacement policy, write policy, and low-power cache memory architecture at the abstract level [1][3][7]. After that, they can write (or modify) a simulation code for their cache memory and test it to check whether or not working properly. This paper is set out explained as follows: Section 2 introduces the procedures for designing a low-power cache memory; Section 3 discusses how to grade the project and provides students’ evaluation; and Section 4 gives the conclusions.

2. Project Procedures

Three major procedures for the class project are design, code, and test. This section shows each procedure in detail. The first step is to design an efficient mapping function for a cache memory to improve system performance. Figure 1 shows three types of cache misses: compulsory misses, capacity misses, and conflict misses. Compulsory misses come from the cold start, the first time accesses; capacity misses depends on the cache sizes; conflict misses are caused by competing one location in a cache

Chu, Y. (2006, June), A Class Project For Low Power Cache Memory Architecture Paper presented at 2006 Annual Conference & Exposition, Chicago, Illinois. https://peer.asee.org/6

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