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A Demonstration Of Cpu Organization Using A Simple Apparatus And 16 People

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Conference

2003 Annual Conference

Location

Nashville, Tennessee

Publication Date

June 22, 2003

Start Date

June 22, 2003

End Date

June 25, 2003

ISSN

2153-5965

Conference Session

Unique Laboratory Experiments & Programs

Page Count

9

Page Numbers

8.40.1 - 8.40.9

Permanent URL

https://peer.asee.org/11861

Download Count

113

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Paper Authors

author page

John Krupczak

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 2526

A Demonstration of CPU Organization Using a Simple Apparatus and Sixteen People

Alexander A. Sherstov, Jr., John J. Krupczak, Jr. Department of Computer Science/Department of Physics and Engineering Hope College Holland, MI 49423

Abstract We have developed a laboratory activity to demonstrate the basic central processing unit (CPU), input, output, and memory of a computer. The activity is intended to help beginning engineering students or non-engineering students to understand basic computer architecture. The activity is based on sixteen individuals who are assigned to conduct specific tasks in a manner analogous to specific computer hardware elements. Tasks assigned to humans include: I/O, memory, control unit, ALU, and registers. The central processing unit consists of five internal registers, an arith- metic/logic unit, and a control unit. These components are interconnected via an internal bus. Bus arbitration is implemented using tri-state buffers. The CPU communicates with memory and the I/O devices through an 8-bit data bus, a 4-bit address bus, and a control bus. The instruction set includes a total of 9 instructions designed to perform arithmetic/logic operations, control flow, and I/O operations involving memory and external devices. Prior to simulation, computer programs are converted to binary code and loaded into memory. Program code comprises a data section and an instruction section. The data section features integers in two’s complement notation. The instruction section is composed of a sequence of fixed-length instructions, each consisting of an identifying 4-bit opcode and an optional 4-bit operand. Operands represent absolute memory addresses. Execution starts at address 0000, which corresponds to the beginning of the instruction section. The fetching and execution of an instruction takes up 4 to 5 phases, each requiring a single CPU cycle. Each phase is characterized by a collection of control signals output by the control unit to the rest of the system. There are a total of 18 distinct phases. The control unit can uniquely determine the next phase from the current phase. Although this system supports only the most basic CPU functionality and lacks many features found in modern CPUs (such as multiple addressing modes, variable-length instructions, and exception handling), it can be effectively used to illustrate a variety of fundamental computing concepts. Among these are the fetch-decode-execute cycle, sequential execution, conditional and unconditional branching, and iteration.

1 Introduction The quality of education in science and technology for all undergraduates is becoming an area of increasing concern [1]. In the United States, the National Science Foundation is requesting that Science, Math, Technology and Engineering (SME&T) programs concentrate more effort on the 80% of college students who are not SME&T majors. In response, science and engineering faculty are developing courses intended to specifically address the needs of the non-SME&T students. A review of some historical background information and relevant new developments

Proceedings of the 2003 American Society for Engineering Education Annual Conference & Exposition Copyright 2003, American Society for Engineering Education

Krupczak, J. (2003, June), A Demonstration Of Cpu Organization Using A Simple Apparatus And 16 People Paper presented at 2003 Annual Conference, Nashville, Tennessee. https://peer.asee.org/11861

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