Qayyum, T. (2009, March), A Junior Level FPGA Course in Digital Design Using Verilog HDL and Altera DE-2 Board For Engineering Technology Students  Paper presented at 2009 Pacific Southwest Section Meeting, National University, San Diego, CA. https://peer.asee.org/52361

\bibitem{asee_peer_52361}
  Qayyum, T. (2009, March), \emph{A Junior Level FPGA Course in Digital Design Using Verilog HDL and Altera DE-2 Board For Engineering Technology Students}
  Paper presented at 2009 Pacific Southwest Section Meeting, National University, San Diego, CA.
  https://peer.asee.org/52361

Tariq Qayyum.  "A Junior Level FPGA Course in Digital Design Using Verilog HDL and Altera DE-2 Board For Engineering Technology Students".  2009 Pacific Southwest Section Meeting, National University, San Diego, CA, 2009, March.  ASEE Conferences, 2009.  https://peer.asee.org/52361 Internet.  22 Feb, 2025

\bibitem{asee_peer_52361}
  Tariq Qayyum.
  "A Junior Level FPGA Course in Digital Design Using Verilog HDL and Altera DE-2 Board For Engineering Technology Students".
  \emph{2009 Pacific Southwest Section Meeting, National University, San Diego, CA, 2009, March}.
  ASEE Conferences, 2009.
  https://peer.asee.org/52361 Internet.  22 Feb, 2025

@INPROCEEDINGS{asee_peer_52361
author = "Tariq Qayyum"
title = "A Junior Level FPGA Course in Digital Design Using Verilog HDL and Altera DE-2 Board For Engineering Technology Students"
booktitle = "2009 Pacific Southwest Section Meeting"
year = "2009"
month = "March"
address = "National University, San Diego, CA"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/52361}
}

TY  - CPAPER
AU  - Tariq Qayyum
CY  - National University, San Diego, CA
DA  - 2009/03/20
PB  - ASEE Conferences
TI  - A Junior Level FPGA Course in Digital Design Using Verilog HDL and Altera DE-2 Board For Engineering Technology Students
UR  - https://peer.asee.org/52361
ER  -