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A Study of Emerging Memory Technology in Hybrid Architectural Approaches of GPGPU

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Conference

2017 Pacific Southwest Section Meeting

Location

Tempe, Arizona

Publication Date

April 20, 2017

Start Date

April 20, 2017

End Date

April 22, 2017

Conference Session

Technical Session 1d

Tagged Topic

Pacific Southwest Section

Page Count

14

Permanent URL

https://peer.asee.org/29201

Download Count

19

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Paper Authors

biography

Reza Raeisi California State University, Fresno

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DR REZA RAEISI is a Professor of Electrical and Computer Engineering Department at California State University, Fresno. He is also Chair of the ECE department. His research interests include integrated circuits, embedded systems, and VLSI-CAD technology. He serves as Pacific Southwest regional director of American Society of Engineering Education. He is an entrepreneur with over 20 years of domestic an international experience and professional skills in both industry and academia. Dr. Raeisi may be reached at rraeisi@csufresno.edu

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biography

Vidya sagar reddy Gopala P.E. California State University, Fresno

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Vidya sagar reddy Gopala received the B.E. in Electronics and Communication from Visvesvaraya Technological University of India (2015). He is currently perusing M.S. in Computer Engineering at California State University,Fresno. He works as teaching and Graduate Assistant in the Department of Electrical and Computer Engineering at California State University, Fresno. His research interests include NOC, VLSI design, system testing, testable design and verification.

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Abstract

Recent trends of drastic improvement speed of the processors have led to application of General Purpose Computing on Graphics Processing Units (GPGPU). We intend to present an educational study of two different hybrid architectural approaches for designing global memories of GPGPUs using different hybridization techniques. We address a hybrid memory organization and design of GPGPU considering emerging memory technology such as Spin Transfer Torque Random Access Memory (STT-RAM), Resistive Random Access Memory (RRAM) and Phase Change Memory (PCM) with conventional Dynamic Random Access (DRAM) memory. PCM memory technology provides inexpensive, fast access time, and high density nonvolatile storage. STT-RAM and RRAM are the new energy-efficient memory alternate for Dynamic and Static Random Access Memory technologies. The General purpose GPU’s global memory consumes a considerable amount of total power of GPGPU. Using hybridization memory organization technique, the leakage power can be scaled to a minimal amount, such that the power and performance can be optimized. We do present the survey on two-hybrid memory architecture approaches that use PCM and combination of RRAM, STT-RAM along with the conventional DRAM memory. We discuss two main issues that designers face while designing hybrid memory architecture approach. A simple flowchart technique will be used to illustrate memory usage behavior and data migration issues that are seen while hybridizing the Global memory of GPGPU. Various memory access patterns will also be discussed in detail. Our primary purpose is to present and share our learning experience obtained through survey with others by highlighting similarities and differences between memory technology, and the current emerging memory technology in GPGPU architecture based on parameters and characteristics.

Raeisi, R., & Gopala, V. S. R. (2017, April), A Study of Emerging Memory Technology in Hybrid Architectural Approaches of GPGPU Paper presented at 2017 Pacific Southwest Section Meeting, Tempe, Arizona. https://peer.asee.org/29201

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