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Reza Raeisi

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Paper listing

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https://peer.asee.org/authors/37392

Co-authors:

A Study of Emerging Memory Technology in Hybrid Architectural Approaches of GPGPU

Conference Session
Technical Session 1d
Collection
2017 Pacific Southwest Section Meeting
Authors
Reza Raeisi, California State University, Fresno; Vidya sagar reddy Gopala P.E., California State University, Fresno

Empirical Learning of Digital Systems Testing and Testable Design Using Industry-Verified Electronics Design Automation Tools in Classroom

Conference Session
Technical Session 3b
Collection
2017 Pacific Southwest Section Meeting
Authors
Reza Raeisi, California State University, Fresno; Vidya sagar reddy Gopala P.E., California State University, Fresno