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An Fpga Project For Use In A Digital Logic Course

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Conference

1999 Annual Conference

Location

Charlotte, North Carolina

Publication Date

June 20, 1999

Start Date

June 20, 1999

End Date

June 23, 1999

ISSN

2153-5965

Page Count

7

Page Numbers

4.70.1 - 4.70.7

Permanent URL

https://peer.asee.org/7683

Download Count

465

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Paper Authors

author page

Thomas Wagner

author page

Daniel C. Gray

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 3226

An FPGA Project for use in a Digital Logic Course

Daniel C. Gray, Thomas D. Wagner United States Military Academy

Abstract

The Digital Computer Logic Course offered at the United States Military Academy teaches cadets the principles of combinational and sequential logic, with an emphasis on programmable logic design. Classroom principles are reinforced with six lab exercises and two projects. In previous versions of the course, cadets were given a digital alarm clock kit that they constructed as credit for one lab.

In 1995, a decision was made to replace the alarm clock with a new project. The new project is a scrolling sign that interfaces through the parallel port of a PC. Two versions of the project have been built, the first using discrete MSI components, and the second using VHDL and a Xilinx FPGA. The FPGA implementation will be used in the future as one of the labs in the Digital Design Course.

This project proved to be a learning experience for the faculty in terms of VHDL, CAD tools, and synthesis onto an FPGA. This paper describes the process of designing the scrolling sign project and the intended use of the project in the EE curriculum at USMA. Lessons learned throughout the process are described as they occurred. The tools used in the design and why they were chosen are described.

I. Introduction

The Digital Computer Logic Course offered at the United States Military Academy teaches cadets the principles of combinational and sequential logic, with an emphasis on programmable logic design. Classroom principles are reinforced with six lab exercises and two projects. In previous versions of the course, cadets were given a digital alarm clock kit that they constructed as credit for one lab.

In 1995, a decision was made to replace the alarm clock with a new project. Two factors contributed to this decision. First, the supplier stopped providing the clock chip used in the design and another supplier could not be found. Second, it was time for a new project for cadets to build in the digital logic course. Two versions of a new project were built. The first version used discrete MSI (medium scale integration) components. The second version of the project used VHDL and a Xilinx FPGA (field programmable gate array).

Existing CAD tools were used to determine if they would support VHDL simulation and synthesis. The first iteration of the VHDL design was simulated in ViewLogic Powerview, synthesized with ViewSynthesis, and mapped onto a Xilinx FPGA using Xilinx Alliance M1.4. Both tools ran on a Sun SPARC1000. For the second iteration of the VHDL design, Xilinx

Wagner, T., & Gray, D. C. (1999, June), An Fpga Project For Use In A Digital Logic Course Paper presented at 1999 Annual Conference, Charlotte, North Carolina. https://peer.asee.org/7683

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