ASEE PEER - Ben Arie Tanay

Ben Arie Tanay

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Integration of VHDL Simulations and Written Reflections to Improve Student Understanding of Sequential Logic Circuits

Conference Session: Digital Circuits, Architecture, Embedded Systems
Collection: 2023 ASEE Annual Conference & Exposition
Authors: Ben Arie Tanay, Purdue Engineering Education; Renee M. Clark, University of Pittsburgh; Gaoxiang Zhou; Samuel J. Dickerson, University of Pittsburgh