Board 21: A Simple SoC Platform for the Integrated Computer Engineering Lab Framework

Pong P. Chu; Chansu Yu; Karla R. Hamlen

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Conference: 2018 ASEE Annual Conference & Exposition
Location: Salt Lake City, Utah
Publication Date: June 23, 2018
Start Date: June 23, 2018
End Date: July 27, 2018
Conference Session: NSF Grantees Poster Session
Tagged Topic: NSF Grantees Poster Session
Page Count: 10
DOI: 10.18260/1-2--29983
Permanent URL: https://peer.asee.org/29983
Download Count: 1067

Paper Authors

biography

Pong P. Chu Cleveland State University

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Dr. Chu is Associate Professor in the Department of Electrical Engineering and Computer Science. He has taught undergraduate and graduate digital systems and computer architecture courses for more than two decades, and he has received multiple instructional grants from the National Science Foundation and authored six textbooks in this area.

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Chansu Yu Cleveland State University

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Chansu Yu received the B.S. and M.S. degrees in electrical engineering from Seoul National University, Korea, in 1982 and 1984, respectively, and the Ph.D. degree in computer engineering from the Pennsylvania State University in 1994. He is currently Professor and Chair of the Department of Electrical Engineering and Computer Science at the Cleveland State University in Cleveland, Ohio. Before joining the CSU, he was on the research staff at LG Electronics, Inc. He has authored/coauthored more than 120 technical papers and numerous book chapters in the areas of mobile computing, performance evaluation, and parallel systems. His research has been supported by both industry and government including National Science Foundation. Dr. Yu is a member of the IEEE, IEEE Computer Society, ACM, and ASEE.

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Karla R. Hamlen Cleveland State University

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Dr. Karla Hamlen is an Associate Professor of Educational Research in the Department of Curriculum and Foundations. She specializes in educational research relating to both formal and informal entertainment technology use among students.

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Abstract

A Simple SoC Platform for the Integrated Computer Engineering Lab Framework

Becoming a good engineer requires the "component skill," which is the knowledge in specific areas, and the "integration skill," which integrates the component skills to solve complex and realistic problems. A study from the Carnegie Foundation recommends a "spiral model" to enhance the integration skills and to provide more effective learning experiences: "... the ideal learning trajectory is a spiral, with all components revisited at increasing levels of sophistication and interconnection. Learning in one area supports learning in another." The grant work is motivated by the spiral model and establishes a lab framework that weaves through the entire computer engineering curriculum, from freshman engineering experiments to senior capstone projects. The framework connects and integrates the individual courses through sound- and video-theme based lab experiments and projects, whose complexities and abstraction levels gradually grow with the progress of curriculum.

The lab framework covers both hardware and software aspects of computer systems and the experiments are done in the SoC (system on a chip) context, in which a system contains a general-purpose processor for “housekeeping” tasks and hardware accelerators for computation-intensive tasks. The commercial SoC platforms are too complex and use the proprietary and encrypted bus interconnect and IP (intellectual property) cores. A simple open and vendor-neutral SoC platform is developed to support the lab framework. It is composed of a synchronous bus, an I/O subsystem, and a video subsystem. The I/O subsystem can accommodate up to 64 IP cores, which can be general-purpose peripherals, such as UART (universal asynchronous receiver and transmitter) core and PWM (pulse width modulation) core, or custom hardware accelerators, such as a sound synthesizer. The subsystem contains a controller that performs address decoding and data multiplexing. The video subsystem can incorporate up to eight video IP cores, which can generate an image, as in a test-pattern generator and on-screen text display, or process an image, as in a color-to-greyscale conversion circuit. The video IP cores include both common bus interface, which is used by the processor to configure the cores, and stream interface, which is used to route the video data stream. The SoC platform can support the audio- and video-theme experiments and projects. It demonstrates many key design concepts and can be used to construct custom and functional embedded systems.

The project is funded by the IUSE program of the Division of Undergraduate Education.

Citation
Format

Chu, P. P., & Yu, C., & Hamlen, K. R. (2018, June), Board 21: A Simple SoC Platform for the Integrated Computer Engineering Lab Framework Paper presented at 2018 ASEE Annual Conference & Exposition , Salt Lake City, Utah. 10.18260/1-2--29983

TY - CPAPER
AB - A Simple SoC Platform for the Integrated Computer Engineering Lab Framework

Becoming a good engineer requires the &quot;component skill,&quot; which is the knowledge in specific areas, and the &quot;integration skill,&quot; which integrates the component skills to solve complex and realistic problems. A study from the Carnegie Foundation recommends a &quot;spiral model&quot; to enhance the integration skills and to provide more effective learning experiences: &quot;... the ideal learning trajectory is a spiral, with all components revisited at increasing levels of sophistication and interconnection. Learning in one area supports learning in another.&quot; The grant work is motivated by the spiral model and establishes a lab framework that weaves through the entire computer engineering curriculum, from freshman engineering experiments to senior capstone projects. The framework connects and integrates the individual courses through sound- and video-theme based lab experiments and projects, whose complexities and abstraction levels gradually grow with the progress of curriculum.

The lab framework covers both hardware and software aspects of computer systems and the experiments are done in the SoC (system on a chip) context, in which a system contains a general-purpose processor for “housekeeping” tasks and hardware accelerators for computation-intensive tasks. The commercial SoC platforms are too complex and use the proprietary and encrypted bus interconnect and IP (intellectual property) cores. A simple open and vendor-neutral SoC platform is developed to support the lab framework. It is composed of a synchronous bus, an I/O subsystem, and a video subsystem. The I/O subsystem can accommodate up to 64 IP cores, which can be general-purpose peripherals, such as UART (universal asynchronous receiver and transmitter) core and PWM (pulse width modulation) core, or custom hardware accelerators, such as a sound synthesizer. The subsystem contains a controller that performs address decoding and data multiplexing. The video subsystem can incorporate up to eight video IP cores, which can generate an image, as in a test-pattern generator and on-screen text display, or process an image, as in a color-to-greyscale conversion circuit. The video IP cores include both common bus interface, which is used by the processor to configure the cores, and stream interface, which is used to route the video data stream. The SoC platform can support the audio- and video-theme experiments and projects. It demonstrates many key design concepts and can be used to construct custom and functional embedded systems.

The project is funded by the IUSE program of the Division of Undergraduate Education.

AU - Pong P. Chu
AU - Chansu Yu
AU - Karla R. Hamlen
CY - Salt Lake City, Utah
DA - 2018/06/23
PB - ASEE Conferences
TI - Board 21: A Simple SoC Platform for the Integrated Computer Engineering Lab Framework
UR - https://peer.asee.org/29983
DO - 10.18260/1-2--29983
ER -