Salt Lake City, Utah
June 23, 2018
June 23, 2018
July 27, 2018
NSF Grantees Poster Session
A Simple SoC Platform for the Integrated Computer Engineering Lab Framework
Becoming a good engineer requires the "component skill," which is the knowledge in specific areas, and the "integration skill," which integrates the component skills to solve complex and realistic problems. A study from the Carnegie Foundation recommends a "spiral model" to enhance the integration skills and to provide more effective learning experiences: "... the ideal learning trajectory is a spiral, with all components revisited at increasing levels of sophistication and interconnection. Learning in one area supports learning in another." The grant work is motivated by the spiral model and establishes a lab framework that weaves through the entire computer engineering curriculum, from freshman engineering experiments to senior capstone projects. The framework connects and integrates the individual courses through sound- and video-theme based lab experiments and projects, whose complexities and abstraction levels gradually grow with the progress of curriculum.
The lab framework covers both hardware and software aspects of computer systems and the experiments are done in the SoC (system on a chip) context, in which a system contains a general-purpose processor for “housekeeping” tasks and hardware accelerators for computation-intensive tasks. The commercial SoC platforms are too complex and use the proprietary and encrypted bus interconnect and IP (intellectual property) cores. A simple open and vendor-neutral SoC platform is developed to support the lab framework. It is composed of a synchronous bus, an I/O subsystem, and a video subsystem. The I/O subsystem can accommodate up to 64 IP cores, which can be general-purpose peripherals, such as UART (universal asynchronous receiver and transmitter) core and PWM (pulse width modulation) core, or custom hardware accelerators, such as a sound synthesizer. The subsystem contains a controller that performs address decoding and data multiplexing. The video subsystem can incorporate up to eight video IP cores, which can generate an image, as in a test-pattern generator and on-screen text display, or process an image, as in a color-to-greyscale conversion circuit. The video IP cores include both common bus interface, which is used by the processor to configure the cores, and stream interface, which is used to route the video data stream. The SoC platform can support the audio- and video-theme experiments and projects. It demonstrates many key design concepts and can be used to construct custom and functional embedded systems.
The project is funded by the IUSE program of the Division of Undergraduate Education.
Chu, P. P., & Yu, C., & Hamlen, K. R. (2018, June), Board 21: A Simple SoC Platform for the Integrated Computer Engineering Lab Framework Paper presented at 2018 ASEE Annual Conference & Exposition , Salt Lake City, Utah. https://peer.asee.org/29983
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