Cadence setup for chip layout

Anu Aggarwal; Shreela Dubey

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Conference: 2024 ASEE North Central Section Conference
Location: Kalamazoo, Michigan
Publication Date: March 22, 2024
Start Date: March 22, 2024
End Date: March 23, 2024
Page Count: 8
DOI: 10.18260/1-2--45598
Permanent URL: https://peer.asee.org/45598
Download Count: 19

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Anu Aggarwal University of Illinois at Urbana - Champaign

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Anu Aggarwal is an Assistant Professor at the University of Illinois, Urbana Champaign. She secured her PhD in Electrical and Computer Engineering from the University of Maryland College Park under the supervision of Prof Robert W Newcomb in the area of N

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Shreela Dubey University of Illinois at Urbana - Champaign

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Abstract

Objective. This paper describes an effort at understanding the cadence flow set up for VLSI design in 180nm technology and updating it to the newer 45nm technology node.

Background. To do any project in cadence, some files need to be set up for cadence license as per the software requirements for the course. Every time the software requirements are updated, or the technology library is updated, the set up files need updating. This project was required because there are over 4 VLSI design courses in our department that use Cadence. When cadence software license was updated to the latest version, the original set up files for all these courses stopped working. IT technologist who used to set up the files for cadence retired at the same time. So, every instructor had to struggle to somehow get the software running for the semester. But there was a need for a long term solution. Therefore, we decided to systematically study the flow set up and learn it to update it to any technology node in future.

Methods. We studied the current setup files for cadence tool for the 180nm technology like the initialization file, library file, simulation file, environment file, and plot initialization files. Thereafter, we downloaded the cell library for 45nm technology node from the cadence website. This library included most of the environment, simulation and design files required for the set up. An initialization script was created that can be run to setup these libraries and files seamlessly. To integrate the update into machine problems for our course, the machine problems (MPs) were updated to utilize the new library. To get students familiar with the environment, we also wrote tutorial files that will help the first-time users to understand the flow. These tutorial files walk through the design, layout, and verification steps. Once the MPs were updated, we tested them to ensure proper integration.

Conclusion. As part of this project, we learned how to set up cadence for any technology library and learned the scripting language for writing the files. This work will be useful for anyone looking to set up a new cadence license for use in circuit design, simulation, layout, and tape out for chip fabrication.

Citation
Format

Aggarwal, A., & Dubey, S. (2024, March), Cadence setup for chip layout Paper presented at 2024 ASEE North Central Section Conference, Kalamazoo, Michigan. 10.18260/1-2--45598

TY - CPAPER
AB - Objective. This paper describes an effort at understanding the cadence flow set up for VLSI design in 180nm technology and updating it to the newer 45nm technology node.

Background. To do any project in cadence, some files need to be set up for cadence license as per the software requirements for the course. Every time the software requirements are updated, or the technology library is updated, the set up files need updating. This project was required because there are over 4 VLSI design courses in our department that use Cadence. When cadence software license was updated to the latest version, the original set up files for all these courses stopped working. IT technologist who used to set up the files for cadence retired at the same time. So, every instructor had to struggle to somehow get the software running for the semester. But there was a need for a long term solution. Therefore, we decided to systematically study the flow set up and learn it to update it to any technology node in future.

Methods. We studied the current setup files for cadence tool for the 180nm technology like the initialization file, library file, simulation file, environment file, and plot initialization files. Thereafter, we downloaded the cell library for 45nm technology node from the cadence website. This library included most of the environment, simulation and design files required for the set up. An initialization script was created that can be run to setup these libraries and files seamlessly. To integrate the update into machine problems for our course, the machine problems (MPs) were updated to utilize the new library. To get students familiar with the environment, we also wrote tutorial files that will help the first-time users to understand the flow. These tutorial files walk through the design, layout, and verification steps. Once the MPs were updated, we tested them to ensure proper integration.

Conclusion. As part of this project, we learned how to set up cadence for any technology library and learned the scripting language for writing the files. This work will be useful for anyone looking to set up a new cadence license for use in circuit design, simulation, layout, and tape out for chip fabrication.

AU - Anu Aggarwal
AU - Shreela Dubey
CY - Kalamazoo, Michigan
DA - 2024/03/22
PB - ASEE Conferences
TI - Cadence setup for chip layout
UR - https://peer.asee.org/45598
DO - 10.18260/1-2--45598
ER -