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Capstone Project: CPU Design with Multiplexer

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Conference

2023 ASEE Annual Conference & Exposition

Location

Baltimore , Maryland

Publication Date

June 25, 2023

Start Date

June 25, 2023

End Date

June 28, 2023

Conference Session

Computing and Information Technology Division (CIT) Technical Session 6

Tagged Division

Computing and Information Technology Division (CIT)

Page Count

7

DOI

10.18260/1-2--43296

Permanent URL

https://peer.asee.org/43296

Download Count

331

Paper Authors

biography

Yumin Zhang Southeast Missouri State University

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Yumin Zhang is a professor in the Department of Engineering and Technology, Southeast Missouri State University. His research interests include semiconductor devices, electronic circuits, neural networks, and engineering education.

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Abstract

Capstone Project: CPU Design with Multiplexer

Abstract

For a capstone design project, we designed and implemented an 8-bit CPU on an Altera DE2 FPGA board. The CPU uses 4-bit opcodes and can execute 16 instructions, including basic arithmetic and logic operations. We simplified the control unit by implementing it with a multiplexer. We fully tested the CPU by inputting instructions and data through the DE2 board switches, and displaying the results on the seven-segment displays and LEDs. This project provides a valuable opportunity for students majoring in electrical engineering and computer science to gain insight into the relationship between machine codes and their corresponding operations.

Zhang, Y. (2023, June), Capstone Project: CPU Design with Multiplexer Paper presented at 2023 ASEE Annual Conference & Exposition, Baltimore , Maryland. 10.18260/1-2--43296

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