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Clocking Schedule And Writing Vhdl Programs For Synthesis

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2004 Annual Conference


Salt Lake City, Utah

Publication Date

June 20, 2004

Start Date

June 20, 2004

End Date

June 23, 2004



Conference Session

Electrical & Computer Engineering Poster Session

Page Count


Page Numbers

9.313.1 - 9.313.15



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Paper Authors

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Chia-Jeng Tseng

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NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1532

Clocking Schedule and Writing VHDL Programs for Synthesis

Chia-Jeng Tseng

Departmentf of Electrical Engineering Bucknell University Lewisburg, Pennsylvania 17837


Most of the commercial tools for digital synthesis are designed for Register-Transfer-Level (RTL) and logic synthesis. Numerous wonderful books and papers are available for understanding the syntax and semantics of the VHDL language. There are also many books and papers written for VHDL synthesis; these articles generally focus on the syntax for describing logic blocks such as combinational circuits, flip-flops, and simple finite state machines as well as how a synthesizer may infer logic from a VHDL description. Most students, even after they have learned the language features, still encounter tremendous difficulty when they begin to use the VHDL to describe a digital system for synthesis. In this paper, we describe the essence of modeling digital functions and present a powerful concept, called clocking schedule, for writing a VHDL program for RTL and logic synthesis. This technique facilitates seamless integration of all the modules in a digital design. A motion-guide project is used to demonstrate the applications and effectiveness of the technique to RTL and logic synthesis using the VHDL. Based on our experience from an “Advanced Digital Design” course, the methodology is very instructive. The students appreciated the power of digital synthesis with the VHDL in a very short period of time.

1. Introduction

Several Electronic Design Automation (EDA) companies 12, 15, 22 offer synthesis tools supporting the VHDL and Verilog languages 2, 3, 5, 7. Most of these programs are designed for RTL and logic synthesis; as a matter of fact, behavioral or high-level synthesis is still in an experimental phase for the design communities. The main difference between high-level synthesis and RTL/logic synthesis is on the conceptual modeling of digital systems.

High-level synthesis assumes a micro-architectural view for digital design. Temporal properties are specified in a description. Clocking signals are, however, not explicitly contained in a behavioral description for high-level synthesis. A description for RTL/logic synthesis, on the other hand, does not contain temporal sequence. Clocking is explicitly specified in a VHDL

“Proceedings of the 2004 American Society for Engineering Education Annual Conference & Exposition Copyright  2004, American Society for Engineering Education”

Tseng, C. (2004, June), Clocking Schedule And Writing Vhdl Programs For Synthesis Paper presented at 2004 Annual Conference, Salt Lake City, Utah. 10.18260/1-2--13028

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