ASEE PEER - Chia-Jeng Tseng

Chia-Jeng Tseng

Paper listing

Permanent URL

https://peer.asee.org/authors/389

Co-authors:

Clocking Schedule And Writing Vhdl Programs For Synthesis

Conference Session: Electrical & Computer Engineering Poster Session
Collection: 2004 Annual Conference
Authors: Chia-Jeng Tseng

Dataflow Scheduling And Exploring Digital System Design Alternatives

Conference Session: ECE Poster Session
Collection: 2006 Annual Conference & Exposition
Authors: Chia-Jeng Tseng, Bucknell University

Efficient Resource Allocation For Fpga Demo Board Based Digital Laboratories

Conference Session: Lab Experiments & Other Initiatives
Collection: 2005 Annual Conference
Authors: Chia-Jeng Tseng

Pedagogic Considerations For Teaching Digital System Design Using Vhdl

Conference Session: New Trends in ECE Education II
Collection: 2007 Annual Conference & Exposition
Authors: Chia-Jeng Tseng, Bucknell University