June 18, 2006
June 18, 2006
June 21, 2006
Electrical and Computer
11.452.1 - 11.452.7
FlexARM1: An ARM Based IP Core for the UP3 Education Kit
Today’s embedded solutions require a rapid product development time to meet strict market demands1. It is essential for system design engineers to verify complex designs in hardware before final implementation. In order for upper level undergraduate students to gain exposure to this verification process, a system level prototyping environment is a necessary tool to provide hands on experience for realizing complex digital systems. System Level Solutions2 and Altera3 offer the UP3 Education Kit as a low cost prototyping platform for system level co hardware/ software development. The UP3 features a powerful Altera Cyclone FPGA4 and an abundance of I/O, peripheral, and memory components allowing for intellectual property (IP) design, prototyping and testing using a hardware descriptive language (HDL).
Modern FPGAs are equipped with features that were not previously available. Today’s FPGAs usually come with phase-locked loops, low-voltage differential signaling, hardware multipliers for DSP, memory, programmable I/O, IP cores, and microprocessor cores5. Because of these features, FPGAs are now a viable choice for the implementation of entire system on a chip, the so-called system-on-a-chip (SoC) concept. HDL design flows using Verilog, VHDL, or SystemC along with today’s advanced logic synthesis tools support the rapid development of these high density programmable SoCs. It is important for students to develop the necessary skills and experience for this emerging technology with the use of available IP cores6, EDA vendor’s logic synthesis tools, and FPGA development boards.
At the heart of every SoC lies a CPU responsible for coordinating the tasks of various components of the system. This paper presents the FlexARM1 processor and its IP design methodology, which could be used as the central core for teaching processor-based systems on FPGAs. This also provides a library of synthesizable VHDL modules for this RISC based CPU, which are currently used in the senior level Computer Architecture course at our institution.
FlexARM1 Design Methodology
The FlexARM1 architecture based on the ARM9 family of commercially available processors developed by ARM7, utilizes the same Harvard architecture and memory mapped I/O concept as the ARM9. The FlexARM1 is a load/store architecture, which implements the following addressing modes from the ARM architecture: data processing immediate shift, data processing register shift, data processing immediate, load/store immediate offset, load/store register offset, and branch and branch with link. All load/store addresses are determined from the register contents and instruction fields only. The FlexARM1 also employs a conditional execution option for each instruction in order to maximize execution throughput. These include fourteen available conditions allowing for the equality and inequality testing of the condition code flags zero, carry, overflow, and negative. The FlexARM1 instruction set is fully compatible with the ARM instruction set. However, time constraints were an issue in implementing every instruction. Some of the more notable instructions not implemented as of
Shaw, B., & Mossayebi, F. (2006, June), Development And Integration Of A Digital Control Laboratory With A Digital System Laboratory At Youngstown State University Paper presented at 2006 Annual Conference & Exposition, Chicago, Illinois. 10.18260/1-2--1020
ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2006 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015