Vurkac, M., & Takach, M. D., & Singh, S. (2024, June), Digital Logic without Compromise in a Quarter-Based EE Curriculum  Paper presented at 2024 ASEE Annual Conference & Exposition, Portland, Oregon. 10.18260/1-2--47191

\bibitem{asee_peer_47191}
  Vurkac, M., \& Takach, M. D., \& Singh, S. (2024, June), \emph{Digital Logic without Compromise in a Quarter-Based EE Curriculum}
  Paper presented at 2024 ASEE Annual Conference \& Exposition, Portland, Oregon.
  10.18260/1-2--47191

Mehmet Vurkac, Margarita D. Takach, and Shruti Singh.  "Digital Logic without Compromise in a Quarter-Based EE Curriculum".  2024 ASEE Annual Conference & Exposition, Portland, Oregon, 2024, June.  ASEE Conferences, 2024.  https://peer.asee.org/47191 Internet.  10 Oct, 2024

\bibitem{asee_peer_47191}
  Mehmet Vurkac, Margarita D. Takach, and Shruti Singh.
  "Digital Logic without Compromise in a Quarter-Based EE Curriculum".
  \emph{2024 ASEE Annual Conference \& Exposition, Portland, Oregon, 2024, June}.
  ASEE Conferences, 2024.
  https://peer.asee.org/47191 Internet.  10 Oct, 2024

@INPROCEEDINGS{asee_peer_47191
author = "Mehmet Vurkac, Margarita D. Takach, and Shruti Singh"
title = "Digital Logic without Compromise in a Quarter-Based EE Curriculum"
booktitle = "2024 ASEE Annual Conference \& Exposition"
year = "2024"
month = "June"
address = "Portland, Oregon"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/47191}
number = {10.18260/1-2--47191}
}

TY  - CPAPER
AB  - Digital Logic without Compromise in a Quarter-Based EE Curriculum
Digital Logic is a course normally required in ECE in curricula everywhere. With the advent of FPGAs, the use of a hardware-description language (HDL) in digital-logic courses has increased significantly. Before this, digital-logic labs used discrete components such as the 7400-series ICs. Since then, most, if not all, discrete-component-based labs have been replaced by HDL labs.
As described in numerous ASEE publications, teaching a hardware-description language (HDL) in a course on digital logic creates significant challenges to student learning, especially in the quarter system. Educators around the world have used various approaches intended to improve student learning. These include having lab exercises created by students who recently (and successfully) took the course, using inductive instruction, and incorporating the use of discrete components along with FPGAs.
The approach taken at our institution to address such challenges is to teach our Digital Logic course first with exclusively hardware-based labs—using discrete components and with in-class and take-home labs and simulations—leaving the HDL aspect to a subsequent two-credit lab course. This approach and the lack of prerequisites allow us to introduce digital logic in the first quarter of the EE curriculum. The following fall, we observe that students do not have extraordinary difficulty learning to program in our choice of HDL. The paper presents the content of the two courses as a model for avoiding the problems of combining the teaching of logic fundamentals with HDLs without compromising either learning objective. Assessment of student learning through challenging applied small-team projects is also discussed, with the basic summarized result that most students, by far, learned both VHDL and basic digital logic to a satisfactory (or better) degree. In addition to project outcomes, this is attested to by students’ overall success in subsequent courses that require the pair of courses in question.
AU  - Mehmet Vurkac
AU  - Margarita D. Takach
AU  - Shruti Singh
CY  - Portland, Oregon
DA  - 2024/06/23
PB  - ASEE Conferences
TI  - Digital Logic without Compromise in a Quarter-Based EE Curriculum
UR  - https://peer.asee.org/47191
DO  - 10.18260/1-2--47191
ER  -