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Electrical Engineering Student Senior Capstone Project: A MOSIS Fast Fourier Transform Processor Chip-Set

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Conference

2011 ASEE Annual Conference & Exposition

Location

Vancouver, BC

Publication Date

June 26, 2011

Start Date

June 26, 2011

End Date

June 29, 2011

ISSN

2153-5965

Conference Session

Capstone Design Projects in ECE

Tagged Division

Electrical and Computer

Page Count

9

Page Numbers

22.548.1 - 22.548.9

DOI

10.18260/1-2--17829

Permanent URL

https://peer.asee.org/17829

Download Count

218

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Paper Authors

biography

Peter M. Osterberg University of Portland

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Dr. Peter Osterberg is an Associate Professor in Electrical Engineering at the University of Portland (Portland, OR). He received his B.S.E.E. and M.S.E.E. degrees from MIT in 1980. He received his Ph.D. degree in electrical engineering from MIT in 1995 in the field of MEMS. He worked in industry at Texas Instruments, GTE, and Digital Equipment Corporation in the field of microelectronics. His research interests are microelectronics, MEMS, and nanoelectronics.

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biography

Aziz Sukru Inan University of Portland

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Dr. Inan is a Professor in the Department of Electrical Engineering and Computer Science in the
School of Engineering at the University of Portland (Portland, OR). He has been on the faculty
since 1989 and was department chair between 1990 and 1996. He received his Ph.D. from
Stanford University in 1983. Dr. Inan has co-authored two textbooks in electromagnetics. His
research interests include Electromagnetics, Electric Circuits and Signals and Systems.

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Abstract

Electrical Engineering Student Senior Capstone Project: A MOSIS 4-Bit, 8-Sample Fast Fourier Transform Processor Chip-SetRecently, for their EE Senior Design Capstone Project, a team of three senior EE studentsfrom the University of Portland (Neil Tuttle, Ziyuan Zhang, and Sandra Pellecer), alongwith their two faculty advisors (Dr. Peter Osterberg and Dr. Aziz Inan) successfullydesigned and simulated a digital 4-bit, 8-sample Fast Fourier Transform Processor circuitand then implemented it as a CMOS VLSI double chip-set and submitted their layout tothe MOSIS Educational Program (MEP) for fabrication and packaging. After receivingthe chip-set back, the students successfully built and tested a functioning Fast FourierTransform prototype system which was presented and demonstrated to the ElectricalEngineering community at the University of Portland. This use of the MEP Program toimplement a sophisticated digital function such as the FFT was an extremely effectivepedagogical experience for the students and the faculty. The MEP program has thepotential to play a crucial role in leveraging EE student projects.The motivation for this design project was as follows. A CMOS 4-bit, 8-sample FastFourier Transform (FFT) chip-set was designed to offload FFT computation results froma microprocessor in order to improve the speed of digital signal processing applications.A double MOSIS chip-set was successfully designed and tested to perform this function.This project was done as part of an undergraduate electrical engineering senior capstonedesign project at the University of Portland. To keep the prototype simple, the inputprecision was limited to four bits per sample and eight samples. Due to the parallelisminherent in “divide-and-conquer” algorithms such as the FFT, a dedicated integratedcircuit can perform the computations more quickly than a general-purposemicroprocessor.The overall system featured a primary PIC microcontroller connected to the MOSIS FFTchip-set, an LCD display, and a secondary PIC microcontroller which acts as an I/Oextender. The primary PIC receives data over the RS-232 protocol from a PC or over theI2C protocol from the secondary PIC’s internal A/D converter. The A/D convertersamples analog input data from an external function generator at 10 kHz, so themaximum frequency on the input is 5 kHz. Next, the primary PIC applies a clock signaland sends data to the MOSIS FFT chip-set. This PIC continues to clock the chip-set untilthe output data is ready. Both PIC microcontrollers receive the resulting data from thechip-set. The second PIC sends its part of the data to the first PIC via the I2C bus. Thefirst PIC formats and displays the data on the LCD. The overall FFT system wassuccessfully demonstrated with a 3.6 kHz sine wave as the input and an 8-sample FFT asthe output. The results were displayed on the LCD. The results were verified usingMATLAB simulation.In conclusion, the 4-bit, 8-sample Fast Fourier Transform chip-set is an effective use ofthe MOSIS Educational Program to implement the Fast Fourier Transform function. It isan example of an extensive application at the undergraduate level. The project achieved“first-silicon” success. This was the first time a design of this scale had been successfullyattempted and completed at the University of Portland.

Osterberg, P. M., & Inan, A. S. (2011, June), Electrical Engineering Student Senior Capstone Project: A MOSIS Fast Fourier Transform Processor Chip-Set Paper presented at 2011 ASEE Annual Conference & Exposition, Vancouver, BC. 10.18260/1-2--17829

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