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Empirical Learning of Digital Systems Testing and Testable Design Using Industry-Verified Electronics Design Automation Tools in Classroom

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Conference

2017 Pacific Southwest Section Meeting

Location

Tempe, Arizona

Publication Date

April 20, 2017

Start Date

April 20, 2017

End Date

April 22, 2017

Conference Session

Technical Session 3b

Tagged Topic

Pacific Southwest Section

Page Count

13

Permanent URL

https://peer.asee.org/29213

Download Count

73

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Paper Authors

biography

Reza Raeisi California State University, Fresno

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DR REZA RAEISI a Professor of Electrical and Computer Engineering Department at California State University, Fresno. He is also Chair of he ECE department. His research interests include integrated circuits, embedded systems, and VLSI-CAD technology. He serves as Pacific Southwest regional director of American Society of Engineering Education. He is an entrepreneur with over 20 years of domestic an international experience and professional skills in both industry and academia. Dr. Raeisi may be reached at rraeisi@csufresno.edu

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biography

Vidya sagar reddy Gopala P.E. California State University, Fresno

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Vidya sagar reddy Gopala received the B.E. in Electronics and Communication from Visvesvaraya Technological University of India (2015). He is currently perusing M.S. in Computer Engineering at California State University,Fresno. He works as teaching and Graduate Assistant in the Department of Electrical and Computer Engineering at California State University, Fresno. His research interests include NOC, VLSI design, system testing, testable design and verification.

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Abstract

The intention of this paper is to introduce and share classroom empirical knowledge on Synopsys TetraMax, an Automatic Test Pattern Generation (ATPG) for design verification and testing of digital logic circuits. TetraMax is an ATPG tool used by the largest innovative silicon companies globally to generate test vectors automatically for design verification of Application-Specific Integrated Circuits (ASIC). TetraMax is the leading tool for generating minimum test patterns possible that covers maximum test coverage for a wide range of designs. The unparalleled ease-of-use and high performance provided by TetraMax allows designers to create efficient, compact test for even the most complex designs in minimal time. Normally, Computer Engineering curriculum does not include courses beyond their fundamental digital logic courses. We have developed a course “Digital Systems Testing and Testable Design”; for students of Computer Engineering who want to be specialized in the design, verification and testing side of VLSI circuits. We will share our knowledge gained through building and configuring Synopsys tools and their application for the design, verification and testing of VLSI circuits in the course. The career field of VLSI verification and test offers excellent opportunities for fresh engineering graduates. Training students to apply theoretical concepts with verified industry tools allows them to gain a deeper level of knowledge of VLSI design, verification and testing. Therefore, enabling them to become career ready upon graduation. This pedagogical experience of course covering the fundamentals of VLSI test process and automatic test equipment (ATE), test economics, faults, fault modeling and fault simulation in conjunction with the empirical learning of Synopsys tools for ATPG will be discussed in the body of the paper along with a results and analysis of a basic example.

Raeisi, R., & Gopala, V. S. R. (2017, April), Empirical Learning of Digital Systems Testing and Testable Design Using Industry-Verified Electronics Design Automation Tools in Classroom Paper presented at 2017 Pacific Southwest Section Meeting, Tempe, Arizona. https://peer.asee.org/29213

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