April 20, 2017
April 20, 2017
April 22, 2017
Pacific Southwest Section
The intention of this paper is to introduce and share classroom empirical knowledge on Synopsys TetraMax, an Automatic Test Pattern Generation (ATPG) for design verification and testing of digital logic circuits. TetraMax is an ATPG tool used by the largest innovative silicon companies globally to generate test vectors automatically for design verification of Application-Specific Integrated Circuits (ASIC). TetraMax is the leading tool for generating minimum test patterns possible that covers maximum test coverage for a wide range of designs. The unparalleled ease-of-use and high performance provided by TetraMax allows designers to create efficient, compact test for even the most complex designs in minimal time. Normally, Computer Engineering curriculum does not include courses beyond their fundamental digital logic courses. We have developed a course “Digital Systems Testing and Testable Design”; for students of Computer Engineering who want to be specialized in the design, verification and testing side of VLSI circuits. We will share our knowledge gained through building and configuring Synopsys tools and their application for the design, verification and testing of VLSI circuits in the course. The career field of VLSI verification and test offers excellent opportunities for fresh engineering graduates. Training students to apply theoretical concepts with verified industry tools allows them to gain a deeper level of knowledge of VLSI design, verification and testing. Therefore, enabling them to become career ready upon graduation. This pedagogical experience of course covering the fundamentals of VLSI test process and automatic test equipment (ATE), test economics, faults, fault modeling and fault simulation in conjunction with the empirical learning of Synopsys tools for ATPG will be discussed in the body of the paper along with a results and analysis of a basic example.
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