Zhu, Z., & Bhowmik, U. K., & Wang, Y., & Cheng, Z., & Chen, Y. W. (2021, July), Having it All: Infusing Parallel Computational Thinking in the Lower-level Computer Engineering Curriculum Using Extended Learning Modules  Paper presented at 2021 ASEE Virtual Annual Conference Content Access, Virtual Conference. 10.18260/1-2--37241

\bibitem{asee_peer_37241}
  Zhu, Z., \& Bhowmik, U. K., \& Wang, Y., \& Cheng, Z., \& Chen, Y. W. (2021, July), \emph{Having it All: Infusing Parallel Computational Thinking in the Lower-level Computer Engineering Curriculum Using Extended Learning Modules}
  Paper presented at 2021 ASEE Virtual Annual Conference Content Access, Virtual Conference.
  10.18260/1-2--37241

Zeran Zhu, Ujjal K. Bhowmik, Yue Wang, Zuofu Cheng, and Yuting W. Chen.  "Having it All: Infusing Parallel Computational Thinking in the Lower-level Computer Engineering Curriculum Using Extended Learning Modules".  2021 ASEE Virtual Annual Conference Content Access, Virtual Conference, 2021, July.  ASEE Conferences, 2021.  https://peer.asee.org/37241 Internet.  15 Dec, 2024

\bibitem{asee_peer_37241}
  Zeran Zhu, Ujjal K. Bhowmik, Yue Wang, Zuofu Cheng, and Yuting W. Chen.
  "Having it All: Infusing Parallel Computational Thinking in the Lower-level Computer Engineering Curriculum Using Extended Learning Modules".
  \emph{2021 ASEE Virtual Annual Conference Content Access, Virtual Conference, 2021, July}.
  ASEE Conferences, 2021.
  https://peer.asee.org/37241 Internet.  15 Dec, 2024

@INPROCEEDINGS{asee_peer_37241
author = "Zeran Zhu, Ujjal K. Bhowmik, Yue Wang, Zuofu Cheng, and Yuting W. Chen"
title = "Having it All: Infusing Parallel Computational Thinking in the Lower-level Computer Engineering Curriculum Using Extended Learning Modules"
booktitle = "2021 ASEE Virtual Annual Conference Content Access"
year = "2021"
month = "July"
address = "Virtual Conference"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/37241}
number = {10.18260/1-2--37241}
}

TY  - CPAPER
AB  - Modifying a course in a well-established program is often challenging due to many factors. First of all, it requires removing a significant portion of the current materials to make room for new topics. In addition, these changes must be reviewed and approved by several layers of committees, which can be a long process. Last but not least, the impact on students could vary widely, depending on their preparation and learning ability and the results would not be known until the changes have been made. 

At the University of Illinois at Urbana-Champaign, a team of faculty and graduate teaching assistants is taking on the challenge of making a curriculum change in lower-level computer engineering courses to infuse parallel computational thinking using extended learning modules. The proposed changes impact three required courses in the curriculum: a 100-level digital logic course, a 200-level introductory programming course, and a 300-level digital systems course. Despite the prevalent use of multi-core and GPUs in computers and handheld devices, parallel and distributed computing education in undergraduate courses is largely absent at the lower levels. This effort identifies current topics in the three courses that could be extended into parallel computing learning modules. These modules are launched at the same time the corresponding course topics are covered, and students are given extra-credit for completing these modules.

This paper focuses on the implementation and assessment of the extended learning modules in the 100-level digital logic course. Two modules were developed and launched in the fall of 2019, one on carry-look-ahead parallel adder and the other on counter with parallel implementation. Each module contains a short-recorded video (under 12 minutes), a set of PowerPoint slides, as well as an asynchronous assessment. Each assessment contains five to six true-or-false, multiple-choice, and fill-in-the-blanks questions. Students are expected to complete each module individually within three weeks of its release date. After completing the adder module, students should be able to: 1) understand the inefficiency of a serial adder; 2) understand the concepts of generate and propagate signals as the basis of carry-look-ahead recursive formulation; 3) express the carry-out recursive expression in terms of inputs. After completing the counter module, students should be able to: 1) recognize a carry-ripple counter and explain its shortcomings; 2) understand that the same approach in carry-look-ahead adder can be used to solve the delay in carry-ripple counter; 3) understand the trade-offs among different parallel counter implementations.

In Fall 2019, 48% (n=183) of students completed the adder module and 47% (n=178) completed the counter module. The completion rate in Spring 2020 and Fall 2020 are 51% (n=144) and 60% (n=215) for the adder module, 52% (n=147) and 60% (n=216) for the counter module, respectively. Besides presenting student assessment data, we will also investigate which group of students by academic achievement are more likely to complete these extended learning opportunities and whether there is a correlation between their performance in these modules and overall performance in the course.
AU  - Zeran Zhu
AU  - Ujjal K. Bhowmik
AU  - Yue Wang
AU  - Zuofu Cheng
AU  - Yuting W. Chen
CY  - Virtual Conference
DA  - 2021/07/26
PB  - ASEE Conferences
TI  - Having it All: Infusing Parallel Computational Thinking in the Lower-level Computer Engineering Curriculum Using Extended Learning Modules
UR  - https://peer.asee.org/37241
DO  - 10.18260/1-2--37241
ER  -