Asee peer logo

Implementation of an 8-bit Low-power Multiplier based on Reversible Gate Technology

Download Paper |

Conference

2014 ASEE Zone 1 Conference

Location

University of Bridgeport, Bridgeport, CT

Publication Date

April 5, 2014

Start Date

April 3, 2014

End Date

April 5, 2014

Page Count

5

Permanent URL

https://peer.asee.org/54044

Download Count

4

Paper Authors

author page

Borui Li

author page

Xiaowei Yu

author page

Bo Zhang

author page

Xingguo Xiong

author page

Lawrence Hmurcik

Download Paper |

Li, B., & Yu, X., & Zhang, B., & Xiong, X., & Hmurcik, L. (2014, April), Implementation of an 8-bit Low-power Multiplier based on Reversible Gate Technology Paper presented at 2014 ASEE Zone 1 Conference, University of Bridgeport, Bridgeport, CT. https://peer.asee.org/54044

ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2014 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015