Improving Verification Skills for a Discrete-Event Simulation Model
- Conference
- Location
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Portland, Oregon
- Publication Date
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June 23, 2024
- Start Date
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June 23, 2024
- End Date
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July 12, 2024
- Conference Session
- Tagged Division
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Industrial Engineering Division (IND)
- Permanent URL
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https://peer.asee.org/47598
Paper Authors
Sima Parisay California State Polytechnic University, Pomona
Dr. Sima Parisay is an Emeritus Professor from the Industrial and Manufacturing Engineering Department at California State Polytechnic University, Pomona, CA. In recent years, she has been a part-time lecturer in the Industrial and System Engineering Department at University of Southern California, Los Angeles, CA. She has 28 years of teaching experience, including creating pedagogical tools to improve the learning process and critical thinking in engineering topics. She is dedicated to not only teaching concepts to students, but also ensuring they acquire important skills useful for their future career endeavors. Outside of the classroom, she has been active, in various capacities, with the Pacific Southwest Section (PSW) of ASEE, American Society for Engineering Education.
She received a B.S. in Industrial Engineering from Sharif University in Iran; M.S. in Production Engineering from Aston University in U.K.; and Ph.D. from Industrial and Systems Engineering at the University of Southern California, in U.S.A.
To reach her, please email: parisay@usc.edu.
Abstract
For over two decades of teaching discrete-event simulation courses, a consistent problem has been noted: most students lack adequate skills needed to verify their simulation models. Compounding this issue is the confusion many students have regarding the distinction between debugging and verification. Most often, professional versions of simulation software, adept at running models and producing output, overlook logical errors. This can lead students to mistakenly believe their models are flawless. Additionally, some students rely solely on animation of their models for verification, which, though helpful, cannot provide the precise and dependable information necessary for a thorough verification process. Unfortunately, existing textbooks and literature often provide limited discussion on model verification, leaving students inadequately prepared.
This paper introduces a set of comprehensive guidelines designed to facilitate the systematic verification of simulation models. To illustrate the practical application of these guidelines, the paper showcases examples. By following these guidelines, students can refine their verification skills and achieve more reliable models, moreover develop critical thinking abilities throughout the process.
This paper also proposes a special-purpose flowchart called a "Logical Model." This model serves a valuable role throughout the simulation process, including: initial system study, model creation, semantic debugging, and verification. The discussion on additional applications of the Logical Model, such as analysis and design of experiments, will be presented in a later paper.
Parisay, S. (2024, June), Improving Verification Skills for a Discrete-Event Simulation Model Paper presented at 2024 ASEE Annual Conference & Exposition, Portland, Oregon. https://peer.asee.org/47598
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