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Session _3647_

Laboratory Development for a VHDL Design Course

George H. Zion Electrical, Computer, and Telecommunication Engineering Technology Rochester Institute of Technology Rochester, NY 14623

Abstract

Due to the proliferation of highly integrated programmable logic devices, (PLD, CPLD, and FPGA), the traditional methods for performing digital logic design has given way to a development process that involves extensive use hardware descriptive languages. In industry, the two languages that have become prominent are VHDL and Verilog.

This paper provides a brief overview of the VHDL hardware descriptive languages and discusses the course and laboratory development for a VHDL design course for the Computer Engineering Technology program at Rochester Institute of Technology.

Proceedings of the 2002 American Society of Engineering Education Annual Conference & Exposition Copyright © 2002, American Society for Engineering Education

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Zion, G. (2002, June), Laboratory Development For A Vhdl Design Course Paper presented at 2002 Annual Conference, Montreal, Canada. 10.18260/1-2--10350