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Lessons And Experiences Of Teaching Vhdl

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Conference

2007 Annual Conference & Exposition

Location

Honolulu, Hawaii

Publication Date

June 24, 2007

Start Date

June 24, 2007

End Date

June 27, 2007

ISSN

2153-5965

Conference Session

Emerging Trends in Engineering Education Poster Session

Page Count

10

Page Numbers

12.1015.1 - 12.1015.10

Permanent URL

https://peer.asee.org/1511

Download Count

213

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Paper Authors

biography

Guoping Wang Indiana University-Purdue University-Fort Wayne (Eng)

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GUOPING WANG is currently Assistant Professor in the Department of Engineering, Indiana University Purdue University Fort Wayne. He teaches courses in digital system design, VLSI Design Lab, and computer architecture.

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Lessons and Experiences of Teaching VHDL

Guoping Wang

Department of Engineering Indiana University Purdue University Fort Wayne

Abstract

VHDL has become an industrial standard language in digital system design. This paper discusses the author’s experience of teaching VHDL to undergraduate engineering students at IPFW. Logic synthesis is focused in the educational activities instead of the complex features of VHDL. Projects which involved synthesis, simulation, implementation and verification using FPGA board were assigned. The pits and falls of teaching and learning of VHDL were discussed. The author’s teaching methodology of VHDL is presented, which is followed by some of the problems that students faced when they were trying to design digital systems using VHDL.

1. Introduction

The VHSIC (Very High Speed Integrated Circuits) Hardware Description Language (VHDL) is a very powerful hardware description language for digital system design. It has become indispensable in electrical and computer engineering programs.

This paper summarizes the main issues that cause learning problems for the students when they are learning to use VHDL to design digital systems. The author’s teaching methodology of VHDL is described in this paper. Instead of introducing the complex features and various statements of VHDL, the synthesizable VHDL models from simple to complex systems were introduced to give the students a good understanding of VHDL.

Most VHDL books use models developed for simulation only and they are armed at practicing engineers. They frequently use language features not supported in synthesized circuit and they are not easy for beginners to read. They seem to confuse students more than help them and end up mixing constructs that are only suitable for synthesis with other VHDL features that should only be used for simulation. Having taught VHDL for several years and used VHDL on several research projects, the author adopted a teaching methodology which is easy for the students to follow. The purpose is trying to help students design synthesizable digital systems instead of some fancy models only for simulation.

2. VHDL Teaching Methodology

When introducing VHDL to the students, it is very important to point out that VHDL is NOT a programming language, it is used for describing the required digital systems. During the teaching activities, the author always drew the relationships between VHDL codes and the

Proceedings of the 2007 American Society for Engineering Education Annual Conference & Exposition Copyright ©2007, American Society for Engineering Education

Wang, G. (2007, June), Lessons And Experiences Of Teaching Vhdl Paper presented at 2007 Annual Conference & Exposition, Honolulu, Hawaii. https://peer.asee.org/1511

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