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Leveraging New Platforms to Provide Students with a Realistic SoC Design Experience

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2016 ASEE Annual Conference & Exposition


New Orleans, Louisiana

Publication Date

June 26, 2016

Start Date

June 26, 2016

End Date

August 28, 2016





Conference Session

Circuits & Systems Education II

Tagged Division

Electrical and Computer

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Paper Authors


Andrew Danowitz California Polytechnic State University, San Luis Obispo Orcid 16x16

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Andrew Danowitz received his PhD in Electrical Engineering from Stanford University in 2014, and is currently an Assistant Professor of Computer Engineering at California Polytechnic State University in San Luis Obispo. His engineering education interests include student mental health, retention, and motivation.

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Antonio Leija California Polytechnic State University, San Luis Obispo

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Antonio Leija is now a Test Engineer at Green Hills Software in Santa Barbara, CA. He attended California Polytechnic University, San Luis Obispo for a master's degree in Electrical Engineering, focusing on embedded systems and digital design.

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Recently there have been a slew of digital design products released that promise to simplify the task of giving students a real-world System-on-Chip (SoC) design experience. These “programmable SoCs” from companies such as Xilinx, Cypress, and Altera combine modern multi-core ARM processors connected to an FPGA through a widely used SoC interconnect standard. This paper discusses a Real Time Embedded System Course I designed that uses the Xilinx Zynq platform to give students first-hand experience with modern System-on-Chip design methodologies and the challenges that designers face in both hardware and software bring-up for a modern IP-based design.

The first portion of this paper discusses how students were trained to use the Zynq platform. The first weeks of the class were dedicated to teaching students the basics of real-time system and custom hardware design. Students used a Zynq-based port of Free-RTOS to learn about Real-time operating systems. Through a series of laboratory assignments, students are taught how to interface the RTOS with custom hardware that they place on the FPGA portion of the chip. The course material developed for this portion of the class will be posted online so that other educators may use it in their teaching.

The second part of this paper discusses some of the projects proposed and completed by students, and any difficulties the students faced along the way. From two weeks into the class, students are asked to form groups of up to four and propose a final project. For their final project, students are required to design and build a complete working system of their choice. Their final project is required to make use of both the processor running RTOS and at least one custom IP block running on the FPGA.

In the final section of this paper I examine student feedback for the course, and comment on some of the challenges I faced in integrating the Zynq PSoC platform, and its corresponding development tools, into the classroom.

Danowitz, A., & Leija, A. (2016, June), Leveraging New Platforms to Provide Students with a Realistic SoC Design Experience Paper presented at 2016 ASEE Annual Conference & Exposition, New Orleans, Louisiana. 10.18260/p.25562

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