June 24, 2007
June 24, 2007
June 27, 2007
Electrical and Computer
12.1149.1 - 12.1149.14
Pedagogic Considerations for Teaching Digital System Design Using VHDL
Over the last four years, system-level design methodologies have been taught in an “Advanced Digital Design” course at Bucknell University. VHDL is used to define the functions and structures of a digital system. The writing of a hardware description is very different from writing a program for software applications. Effective teaching of a hardware description language such as VHDL is a challenging task. To improve the effectiveness of teaching digital system design using VHDL, numerous pedagogic considerations have been taken into account. In this paper major pedagogic considerations including course organization and materials are described. Student feedback was collected and analyzed; the effectiveness of each course module is reviewed. Common mistakes and general guidelines of writing VHDL descriptions for synthesis are also presented.
Two digital design courses are offered at Bucknell University: one is entitled “Digital System Design” and the other is called “Advanced Digital Design.” Both courses consist of three hours of lectures and laboratories weekly. Digital System Design, offered to the junior class, focuses on logic synthesis; schematic capture is used for design entry. “Advanced Digital Design,” offered to senior and graduate students, addresses system- level design methodologies; the detailed breakdown consists of VHDL, register-transfer- level design methodologies, advanced topics in logic synthesis, and technology mapping. This paper addresses the pedagogic considerations of teaching “Advanced Digital Design” using VHDL.
The design description of a digital system may contain a number of combinational logic blocks, flip-flops, counters, finite state machines, embedded finite state machines, and register-transfer-level function blocks such as registers, multiplexers as well as arithmetic and logic units. The VHDL description of a module can be written in dataflow, behavioral, or structural style. These module descriptions can be bundled together and randomly placed in a design description.
Based on the basic digital components, the issues of writing a VHDL description to specify a digital system are addressed in Section 2. Section 3 discusses system-level design issues. Section 4 describes laboratory and project assignments for students to practice digital design methodologies using VHDL. Section 5 presents common mistakes of and general guidelines for writing VHDL descriptions for synthesis. Finally, the results of course assessment and concluding remarks are presented in Section 6.
Tseng, C. (2007, June), Pedagogic Considerations For Teaching Digital System Design Using Vhdl Paper presented at 2007 Annual Conference & Exposition, Honolulu, Hawaii. 10.18260/1-2--2065
ASEE holds the copyright on this document. It may be read by the public free of charge. Authors may archive their work on personal websites or in institutional repositories with the following citation: © 2007 American Society for Engineering Education. Other scholars may excerpt or quote from these materials with the same citation. When excerpting or quoting from Conference Proceedings, authors should, in addition to noting the ASEE copyright, list all the original authors and their institutions and name the host city of the conference. - Last updated April 1, 2015