Teaching Computer Architecture Using VHDL Simulation and FPGA Prototyping

Ronald J. Hayne

Download Paper | Permalink

Conference: 2024 ASEE Annual Conference & Exposition
Location: Portland, Oregon
Publication Date: June 23, 2024
Start Date: June 23, 2024
End Date: July 12, 2024
Conference Session: Computer Engineering Topics
Tagged Division: Computers in Education Division (COED)
Tagged Topic: Diversity
Permanent URL: https://peer.asee.org/48059

Request a correction

Paper Authors

biography

Ronald J. Hayne The Citadel

visit author page

Ronald J. Hayne is a Professor in the Department of Electrical and Computer Engineering at The Citadel. He received his B.S. in Computer Science from the United States Military Academy, his M.S. in Electrical Engineering from the University of Arizona, and his Ph.D. in Electrical Engineering from the University of Virginia. Dr. Hayne's professional areas of interest include digital systems design and hardware description languages. He is a retired Army Colonel with experience in academics and Defense laboratories.

visit author page

Download Paper | Permalink

Abstract

Teaching computer architecture involves use of many digital components including counters, registers, multiplexers, ALUs, and memory. The design of a computer processor combines these building blocks into an integrated digital system. An Instructional Processor, developed as a design example in an Advanced Digital Systems course, has been expanded to facilitate teaching a graduate Computer Architecture course. The design is modelled in VHDL and can be simulated using Xilinx design tools. A basic microcontroller is created by adding memory-mapped input/output (I/O). The system can be implemented in hardware on a field programmable gate array (FPGA) and interfaced with multiple peripheral devices.

The course starts with an introduction/review of VHDL by modelling key components of the processor architecture, the program counter and multi-port register file. Students gain insights into VHDL design techniques and familiarity with the Xilinx tools. More advanced sequential systems are designed via a control unit directing a dedicated datapath. This technique is critical for complexity management and serves as the basis for the processor architecture. Throughout the VHDL lessons, the importance of specific modelling constructs and their relation to synthesized hardware are emphasized. This ensures that after successful simulation, the processor design can be implemented and tested in hardware.

The datapath of the Instructional Processor combines the previously developed components with an ALU, registers, buses, and memory. The instruction set architecture is designed using basic operations and addressing modes with sufficient complexity to demonstrate fundamental programming concepts such as data transfer, counting, indexing, and looping. Programs are written in assembly language and converted to machine language with the provided assembler. The VHDL model interconnects the datapath components with their appropriate control signals. The control unit then generates the necessary sequence of commands to fetch, decode, and execute the machine language program. The system is tested using simulation to verify proper operation via register values, ALU results, control signals, and memory contents.

A key component of the course is a student design project. The Instructional Processor provides the base design, which is modified to adapt to a new set of specifications. The register file is expanded to allow implementation of a load and store architecture with new instructions and formats. Students must modify the appropriate processor components and integrate them into the datapath. The control unit must also be redesigned to accommodate the new instructions. The sample test program is converted to the new assembly language, encoded in machine code, and tested via simulation of the updated VHDL model.

While the students are working on their design projects, the class continues with expansion of the base processor design. A microcontroller is created by adding memory-mapped I/O and the system is synthesized to an FPGA. A pulse-width-modulation (PWM) motor control demonstration is used to test the prototype hardware. Next, a serial communication interface is designed using a universal asynchronous receiver transmitter (UART). Finally, a programmable timer and interrupt system are added to the processor architecture. The enhanced FPGA microcontroller is tested using a time-multiplexed display and a serial radio frequency identification (RFID) card reader. The design example gives students an in-depth look at both the internal details and external interfacing of a real-life system.

The new graduate course has successfully used the expanded Instructional Processor to teach Computer Architecture using VHDL modelling and simulation, combined with FPGA implementation and testing. The design project serves as a good assessment of the students’ understanding of key design concepts via their use of industry-standard tools. Feedback has been very positive that the course illustrates fundamental design concepts reinforced by actual functioning hardware.

Citation
Format

Hayne, R. J. (2024, June), Teaching Computer Architecture Using VHDL Simulation and FPGA Prototyping Paper presented at 2024 ASEE Annual Conference & Exposition, Portland, Oregon. https://peer.asee.org/48059

TY - CPAPER
AB - Teaching computer architecture involves use of many digital components including counters, registers, multiplexers, ALUs, and memory. The design of a computer processor combines these building blocks into an integrated digital system. An Instructional Processor, developed as a design example in an Advanced Digital Systems course, has been expanded to facilitate teaching a graduate Computer Architecture course. The design is modelled in VHDL and can be simulated using Xilinx design tools. A basic microcontroller is created by adding memory-mapped input/output (I/O). The system can be implemented in hardware on a field programmable gate array (FPGA) and interfaced with multiple peripheral devices.

The course starts with an introduction/review of VHDL by modelling key components of the processor architecture, the program counter and multi-port register file. Students gain insights into VHDL design techniques and familiarity with the Xilinx tools. More advanced sequential systems are designed via a control unit directing a dedicated datapath. This technique is critical for complexity management and serves as the basis for the processor architecture. Throughout the VHDL lessons, the importance of specific modelling constructs and their relation to synthesized hardware are emphasized. This ensures that after successful simulation, the processor design can be implemented and tested in hardware.

The datapath of the Instructional Processor combines the previously developed components with an ALU, registers, buses, and memory. The instruction set architecture is designed using basic operations and addressing modes with sufficient complexity to demonstrate fundamental programming concepts such as data transfer, counting, indexing, and looping. Programs are written in assembly language and converted to machine language with the provided assembler. The VHDL model interconnects the datapath components with their appropriate control signals. The control unit then generates the necessary sequence of commands to fetch, decode, and execute the machine language program. The system is tested using simulation to verify proper operation via register values, ALU results, control signals, and memory contents.

A key component of the course is a student design project. The Instructional Processor provides the base design, which is modified to adapt to a new set of specifications. The register file is expanded to allow implementation of a load and store architecture with new instructions and formats. Students must modify the appropriate processor components and integrate them into the datapath. The control unit must also be redesigned to accommodate the new instructions. The sample test program is converted to the new assembly language, encoded in machine code, and tested via simulation of the updated VHDL model.

While the students are working on their design projects, the class continues with expansion of the base processor design. A microcontroller is created by adding memory-mapped I/O and the system is synthesized to an FPGA. A pulse-width-modulation (PWM) motor control demonstration is used to test the prototype hardware. Next, a serial communication interface is designed using a universal asynchronous receiver transmitter (UART). Finally, a programmable timer and interrupt system are added to the processor architecture. The enhanced FPGA microcontroller is tested using a time-multiplexed display and a serial radio frequency identification (RFID) card reader. The design example gives students an in-depth look at both the internal details and external interfacing of a real-life system.

The new graduate course has successfully used the expanded Instructional Processor to teach Computer Architecture using VHDL modelling and simulation, combined with FPGA implementation and testing. The design project serves as a good assessment of the students’ understanding of key design concepts via their use of industry-standard tools. Feedback has been very positive that the course illustrates fundamental design concepts reinforced by actual functioning hardware.

AU - Ronald J. Hayne
CY - Portland, Oregon
DA - 2024/06/23
PB - ASEE Conferences
TI - Teaching Computer Architecture Using VHDL Simulation and FPGA Prototyping
UR - https://peer.asee.org/48059
ER -