June 26, 2011
June 26, 2011
June 29, 2011
Electrical and Computer
22.1386.1 - 22.1386.6
Teaching Digital Systems Verification Methodologies using SystemVerilogWith the growing complexity of modern digital system and embedded system designs,the task of verification has become the key to achieving the faster time-to-marketrequirement for such designs. This paper describes a graduate level course, offered atBoise State University as a part of the Masters of Science program in ComputerEngineering, in Verification of Digital System designs using SystemVerilog. This coursedoes not only teach syntax and semantics but also a coverage-driven, constrained random,and assertion based verification methodologies employing the advanced features ofSystemVerilog to ensure that the designs meet given design specifications. The coursealso emphasizes the practical aspects of verifications through providing the studentshands-on experience on commercial verification tools such as QuestaSim AdvancedFunctional Verification from Mentor Graphic's Advanced Verification Environment. The short-term and long-term goals of the course are explained along with the course content andformat. The course is designed around small projects to illustrate the main concepts,tools, and language usage. A mid-term and a final project are also offered that require anautomated verification environment to be designed and tested.
Rafla, N. (2011, June), Teaching Digital Systems Verification Methodologies using SystemVerilog Paper presented at 2011 ASEE Annual Conference & Exposition, Vancouver, BC. https://peer.asee.org/18558
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