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Teaching Digital Systems Verification Methodologies using SystemVerilog

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2011 ASEE Annual Conference & Exposition


Vancouver, BC

Publication Date

June 26, 2011

Start Date

June 26, 2011

End Date

June 29, 2011



Conference Session

ECE Division Poster Session

Tagged Division

Electrical and Computer

Page Count


Page Numbers

22.1386.1 - 22.1386.6

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Paper Authors


Nader Rafla Boise State University

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Dr. Nader Rafla, P.E., received his M.S.E.E. and Ph.D. in Electrical Engineering from Case Western Reserve University, Cleveland, Ohio in 1984 and 1991 respectively. His Doctoral research concentrated on object recognition and localization from range image data, force-torque, and touch sensors data.

From 1991 to 1996, he was an Associate Professor in the department of Manufacturing Engineering at the Central State University. Where he taught courses related to the electrical engineering component of the program. In the mean time, he developed and was involved in a research program in applied image processing.

In January, 1997, He joined the newly developed electrical and computer engineering program at Boise State University where he is currently an Associate professor and chair of the Electrical Engineering Department. He led the development and starting of the M.S. of Computer Engineering; He taught several courses and supervised numerous M.S. thesis and Senior Design Projects. He also has conducted research and consulted in R&D for Micron Technology, Hewlett Packard and others.

Dr. Rafla’s area of expertise is systems on a programmable chip and embedded & microprocessor-based system design; Evolvable and self-reconfigurable systems; and implementation and hardware architectures of digital image and signal processing algorithms applied to recognition, identification, inspection, automation and control. He is a senior member of the IEEE organization and several societies and a member of the ASEE organization.

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Teaching Digital Systems Verification Methodologies using SystemVerilogWith the growing complexity of modern digital system and embedded system designs,the task of verification has become the key to achieving the faster time-to-marketrequirement for such designs. This paper describes a graduate level course, offered atBoise State University as a part of the Masters of Science program in ComputerEngineering, in Verification of Digital System designs using SystemVerilog. This coursedoes not only teach syntax and semantics but also a coverage-driven, constrained random,and assertion based verification methodologies employing the advanced features ofSystemVerilog to ensure that the designs meet given design specifications. The coursealso emphasizes the practical aspects of verifications through providing the studentshands-on experience on commercial verification tools such as QuestaSim AdvancedFunctional Verification from Mentor Graphic's Advanced Verification Environment. The short-term and long-term goals of the course are explained along with the course content andformat. The course is designed around small projects to illustrate the main concepts,tools, and language usage. A mid-term and a final project are also offered that require anautomated verification environment to be designed and tested.

Rafla, N. (2011, June), Teaching Digital Systems Verification Methodologies using SystemVerilog Paper presented at 2011 ASEE Annual Conference & Exposition, Vancouver, BC.

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