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Undergraduate Research In Nanotechnology Circuit Design

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Conference

2004 Annual Conference

Location

Salt Lake City, Utah

Publication Date

June 20, 2004

Start Date

June 20, 2004

End Date

June 23, 2004

ISSN

2153-5965

Conference Session

Undergraduate Research & New Directions

Page Count

11

Page Numbers

9.1337.1 - 9.1337.11

Permanent URL

https://peer.asee.org/12797

Download Count

48

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Paper Authors

author page

Aranggan Venkataratnam

author page

Ashok Goel

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Abstract
NOTE: The first page of text has been automatically extracted and included below in lieu of an abstract

Session 1332

Undergraduate Research in Nanotechnology Circuit Design

Ashok Goel, Constance Rimatzki, Dean Gores and Aranggan Venkataratnam

Department of Electrical & Computer Engineering Michigan Technological University Houghton, MI 49931

Abstract Undergraduate research in the area of nanotechnology circuit design is described. Two undergraduate students worked with electrical engineering graduate students and a faculty member on projects related to designing nanoscale logic gates and circuits using single electron transistors and by using quantum cells. In this paper, the undergraduate research projects carried out by the two REU students are summarized

1. Introduction

Active research experience is one of the most effective techniques for training and motivating undergraduate students for careers in science and engineering. National Science Foundation (NSF) recognizes this and supports undergraduate research under “Research Experiences for Undergraduates (REU) Supplements” program where it encourages principal investigators of NSF-funded research grants to include one or two undergraduate students in their existing projects. This paper summarizes the experiences of two such REU students (CR, DG) who worked on research projects in nanotechnology circuit design under the supervision of graduate students (AV and others) and faculty (AG).

The semiconductor industry has been constantly working on shrinking the size of the MOSFET to increase the device density and data transfer rate for the integrated circuit. The cur rent trend of MOSFET scaling may fall apart when the transistor sizes are shrunk to a few nanometers. At the nanometer scale, quantum behaviors come into effect and cause undesirable effects such as subthreshold leakage, gate oxide leakage, increased transistor parameter variability and interconnect density and performance. In order to overcome these hurdles for producing high density chips with low power consumption, some of the devices in the nanometer scale that are being studied by research groups as possible replacements for MOSFETs include carbon nanotube transistors, nanowire FETs, single electron transistors (SET) [1-11] and quantum dots [12-14].

One of the REU students (CR) worked on a project whose goal was to extend the widely used MOSFET-based CMOS technology to designing CMOS logic gates using the single electron transistor technology. First, she learnt the physics of these devices and their

“Proceedings of the 2004 American Society for Engineering Education Annual Conference & Exposition Copyright 2004, American Society for Engineering Education”

Venkataratnam, A., & Goel, A. (2004, June), Undergraduate Research In Nanotechnology Circuit Design Paper presented at 2004 Annual Conference, Salt Lake City, Utah. https://peer.asee.org/12797

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