Carrano, M., & Koziol, S., & Chabot, E., & Boline, J., & DiCecco, J. (2021, March), FPGA/MATLAB Hardware in the Loop Testbed for Stochastic Artificial Neural Networks  Paper presented at ASEE 2021 Gulf-Southwest Annual Conference, Waco, Texas. 10.18260/1-2--36380

\bibitem{asee_peer_36380}
  Carrano, M., \& Koziol, S., \& Chabot, E., \& Boline, J., \& DiCecco, J. (2021, March), \emph{FPGA/MATLAB Hardware in the Loop Testbed for Stochastic Artificial Neural Networks}
  Paper presented at ASEE 2021 Gulf-Southwest Annual Conference, Waco, Texas.
  10.18260/1-2--36380

Matthew Carrano, Scott Koziol, Eugene Chabot, Jacob Boline, and John DiCecco.  "FPGA/MATLAB Hardware in the Loop Testbed for Stochastic Artificial Neural Networks".  ASEE 2021 Gulf-Southwest Annual Conference, Waco, Texas, 2021, March.  ASEE Conferences, 2021.  https://peer.asee.org/36380 Internet.  24 Apr, 2024

\bibitem{asee_peer_36380}
  Matthew Carrano, Scott Koziol, Eugene Chabot, Jacob Boline, and John DiCecco.
  "FPGA/MATLAB Hardware in the Loop Testbed for Stochastic Artificial Neural Networks".
  \emph{ASEE 2021 Gulf-Southwest Annual Conference, Waco, Texas, 2021, March}.
  ASEE Conferences, 2021.
  https://peer.asee.org/36380 Internet.  24 Apr, 2024

@INPROCEEDINGS{asee_peer_36380
author = "Matthew Carrano, Scott Koziol, Eugene Chabot, Jacob Boline, and John DiCecco"
title = "FPGA/MATLAB Hardware in the Loop Testbed for Stochastic Artificial Neural Networks"
booktitle = "ASEE 2021 Gulf-Southwest Annual Conference"
year = "2021"
month = "March"
address = "Waco, Texas"
publisher = "ASEE Conferences"
note = {https://peer.asee.org/36380}
number = {10.18260/1-2--36380}
}

TY  - CPAPER
AB  - Abstract—This paper presents a Hardware in the Loop (HWIL) testbed for evaluating a Stochastic Artificial Neural Network (SANN). The SANN is implemented in a Field Programmable Gate Array (FPGA), and this testbed allows test data to be generated on a computer using MATLAB, and sent to the FPGA SANN over a Universal Asynchronous Receiver/Transmitter (UART) interface. Initial hardware results are presented.
AU  - Matthew Carrano
AU  - Scott Koziol
AU  - Eugene Chabot
AU  - Jacob Boline
AU  - John DiCecco
CY  - Waco, Texas
DA  - 2021/03/24
PB  - ASEE Conferences
TI  - FPGA/MATLAB Hardware in the Loop Testbed for Stochastic Artificial Neural Networks
UR  - https://peer.asee.org/36380
DO  - 10.18260/1-2--36380
ER  -