June 14, 2015
June 14, 2015
June 17, 2015
Electrical and Computer
26.1082.1 - 26.1082.12
Less is More: Developing complex designs using a minimal HDL subset in an introductory digital devices laboratory While the core knowledge composing a traditional introductory course on digital devices (Boolean algebra, finite state machines) has been stable for some time, several recent trends challenge educators. First, the move from older PLDs such as the classic 22V10 PAL to more complex FPGAs requires a transition from relatively simple hardware description languages (HDLs) such as PALASM or ABEL to the significant complexity of modern HDLs such as Verilog or VHDL, which professional design engineers spend years to master. Second, the wide availability of high gate count FPGAs enables students to create amazingly complex designs involving datapath components such as adders and counters. This twofold increase in complexity requires a redesign of the traditional introductory digital design laboratory to enable students to create complex designs using a relative simple design methodology. Therefore, this paper proposes the use of a minimal subset of an HDL (Verilog, in this case) complemented by judicious use of schematic capture and its library of datapath components to enable students to create modern, registertransfer level (RTL) driven designs without requiring students to develop a deep expertise in an HDL. In addition, the use of assertions supported by newer HDLs provides students with immediate feedback on the correctness of their designs, a vital feature which enables them to succeed in the creation of complex designs. The figure on the following page provides an illustration of the approach developed in this paper. This laboratory exercise challenges students to design a 4bit, 16entry queue. First, in (1) schematic capture allows students to easily instantiate complex library components (dualport RAM, counters, etc.). Second, the detail of the controller block’s design in (2) shows the layout of a simple FSM: D flipflops are taken from the library, while combinational logic is implemented using Verilog’s continuous assignment statements in (3). Finally, the test bench shown below is provided to students, enabling them to verify the correctness of their design. Notice the progression of concepts in this diagram: first, combinational logic is introduced. Coupling this with D flipflops then enables FSM design. Next, the use of datapath components as library symbols introduces students to RTL design. Finally, coupling that datapath with an FSM provides a full RTLcentric design experience. In conclusion, this straightforward approach of implementing combinational logic using a Verilog assign statement, then employing simple hierarchical design techniques and making use of library blocks for datapath components provides instructors with a flexible toolkit, helping students master the complexity of modern digital design.
Jones, B. A., & Moorhead, J. N., & Mohammadi-Aragh, M. J. (2015, June), Less is More: Developing Complex Designs Using a Minimal HDL Subset in an Introductory Digital Devices Laboratory Paper presented at 2015 ASEE Annual Conference & Exposition, Seattle, Washington. 10.18260/p.24419
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