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Less is More: Developing Complex Designs Using a Minimal HDL Subset in an Introductory Digital Devices Laboratory

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2015 ASEE Annual Conference & Exposition


Seattle, Washington

Publication Date

June 14, 2015

Start Date

June 14, 2015

End Date

June 17, 2015





Conference Session

Computer Science, Computer Engineering, and Digital Systems Education 1

Tagged Division

Electrical and Computer

Page Count


Page Numbers

26.1082.1 - 26.1082.12



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Paper Authors


Bryan A. Jones Mississippi State University

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Bryan A. Jones (S’00–M’00) received the B.S.E.E. and M.S. degrees in electrical engineering from Rice University, Houston, TX, in 1995 and 2002, respectively, and the Ph.D. degree in electrical engineering from Clemson University, Clemson, SC, in 2005. He is currently an Assistant Professor with the Mississippi State University, Mississippi State, MS.

From 1996 to 2000, he was a Hardware Design Engineer with Compaq, where he specialized in board layout for high-availability redundant array of independent disks (RAID) controllers. His current research interests include robotics, real-time control-system implementation, rapid prototyping for real-time systems, and modeling and analysis of mechatronic systems

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Jane Nicholson Moorhead Mississippi State University


M. Jean Mohammadi-Aragh Mississippi State University Orcid 16x16

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Dr. M. Jean Mohammadi-Aragh is an assistant research professor with a joint appointment in the Bagley College of Engineering dean’s office and the Department of Electrical and Computer Engineering at Mississippi State University. Through her role in the Hearin Engineering First-year Experiences (EFX) Program, she is assessing the college’s current first-year engineering efforts, conducting rigorous engineering education research to improve first-year experiences, and promoting the adoption of evidence-based instructional practices. In addition to research in first year engineering, Dr. Mohammadi-Aragh investigates technology-supported classroom learning and using scientific visualization to improve understanding of complex phenomena. She earned her Ph.D. (2013) in Engineering Education from Virginia Tech, and both her M.S. (2004) and B.S. (2002) in Computer Engineering from Mississippi State. In 2013, Dr. Mohammadi-Aragh was honored as a promising new engineering education researcher when she was selected as an ASEE Educational Research and Methods Division Apprentice Faculty.

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Less is More: Developing complex designs using a minimal  HDL subset in an introductory digital devices laboratory  While the core knowledge composing a traditional introductory course on digital devices (Boolean algebra, finite state machines) has been stable for some time, several recent trends challenge educators. First, the move from older PLDs such as the classic 22V10 PAL to more complex FPGAs requires a transition from relatively simple hardware description languages (HDLs) such as PALASM or ABEL to the significant complexity of modern HDLs such as Verilog or VHDL, which professional design engineers spend years to master. Second, the wide availability of high gate count FPGAs enables students to create amazingly complex designs involving datapath components such as adders and counters. This two­fold increase in complexity requires a redesign of the traditional introductory digital design laboratory to enable students to create complex designs using a relative simple design methodology.  Therefore, this paper proposes the use of a minimal subset of an HDL (Verilog, in this case) complemented by judicious use of schematic capture and its library of datapath components to enable students to create modern, register­transfer level (RTL) driven designs without requiring students to develop a deep expertise in an HDL. In addition, the use of assertions supported by newer HDLs provides students with immediate feedback on the correctness of their designs, a vital feature which enables them to succeed in the creation of complex designs.  The figure on the following page provides an illustration of the approach developed in this paper. This laboratory exercise challenges students to design a 4­bit, 16­entry queue. First, in (1) schematic capture allows students to easily instantiate complex library components (dual­port RAM, counters, etc.). Second, the detail of the controller block’s design  in (2) shows the layout of a simple FSM: D flip­flops are taken from the library, while combinational logic is implemented using Verilog’s continuous assignment statements in (3). Finally, the test bench shown below is provided to students, enabling them to verify the correctness of their design.  Notice the progression of concepts in this diagram: first, combinational logic is introduced. Coupling this with D flip­flops then enables FSM design. Next, the use of datapath components as library symbols introduces students to RTL design. Finally, coupling that datapath with an FSM provides a full RTL­centric design experience.  In conclusion, this straightforward approach of implementing combinational logic using a Verilog assign statement, then employing simple hierarchical design techniques and making use of library blocks for datapath components provides instructors with a flexible toolkit, helping students master the complexity of modern digital design.  

Jones, B. A., & Moorhead, J. N., & Mohammadi-Aragh, M. J. (2015, June), Less is More: Developing Complex Designs Using a Minimal HDL Subset in an Introductory Digital Devices Laboratory Paper presented at 2015 ASEE Annual Conference & Exposition, Seattle, Washington. 10.18260/p.24419

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