Neuromorphic VLSI design course

Anu Aggarwal

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Conference: 2022 ASEE Annual Conference & Exposition
Location: Minneapolis, MN
Publication Date: August 23, 2022
Start Date: June 26, 2022
End Date: June 29, 2022
Conference Session: Curricular Developments in Electrical and Computer Engineering
Page Count: 14
DOI: 10.18260/1-2--40674
Permanent URL: https://peer.asee.org/40674
Download Count: 733

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Anu Aggarwal University of Illinois at Urbana - Champaign

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Abstract

This paper describes a novel Neuromorphic VLSI design course that was added to the Electrical and Computer Engineering curriculum at **** university. Significance: Neuromorphic VLSI design has been a research area for over 3 decades. It started with attempts to build silicon chips that could emulate functions of various brain regions like eye and cochlea [1]. With Moore’s law hitting physical limits, the industry is looking to improve silicon circuit efficiency by exploring better algorithms like neurally inspired (Neuromorphic). This includes Intel’s foray into building neuromorphic chip, the Loihi [2]. This follows another neuromorphic chip by IBM, the True North [3]. The True North is a neural processor with arrays of neurons and synapses. In addition to being a neural processor, the Loihi chip facilitates learning dynamically like the human brain. These chips can not only be used to emulate areas of the brain but also to build dedicated machine learning hardware [4] and to build neural prosthesis. Despite so many avenues, very few universities offer such a course. Therefore, we decided to offer this course at our university. This course includes teaching low power design, subthreshold mode circuits, mixed-signal chips and combining multiple chips into a system to realize neuromorphic hardware. Background: Computational elements of neuromorphic circuits are MOSFETs in sub-threshold mode operation. MOSFETs exhibit exponential I-V characteristics and low currents when operating in this mode. Memory is implemented locally within the individual computational elements like floating gates and MITES. These properties lead to the feasibility of high-density, low-power implementation of functions that are computationally intensive in other paradigms. Curriculum: similar courses at Georgia Tech [5] and at the Institute of Neuroinformatics (INI), ETH Zurich [6] were studied. Based on these, topics studied were: MOS transistors in CMOS technology, floating gates, static circuits, dynamic circuits, systems (silicon neuron-synapse arrays, silicon retina, silicon cochlea, silicon hippocampus, silicon lateral superior olive) with an introduction to multi-chip systems that communicate events analogous to spikes. Course project: building retinal chip circuits and testing them using image data. This course was targeted at seniors and graduate students interested in machine learning, mixed-signal low-power VLSI design and neural engineering. It was a 3-credit lecture course. Grading was based on homework (20%), project (30%), midterm (20%) and final (30%) exams. Reference materials: Analog VLSI: Circuits and Principles (Shih-Chii Liu, et. al., 2002), Analog VLSI and Neural systems (Carver Mead, 1989), and readings. Syllabus Course review Long term vision References [1] Mead, Carver (1989). Analog VLSI and Neural Systems. Addison-Wesley, Reading, MA. ISBN 0201059924. [2] https://www.intel.com/content/www/us/en/research/neuromorphic-computing.html [3] D. Modha (2014). Introducing a Brain-inspired Computer TrueNorth's neurons to revolutionize system architecture. < https://research.ibm.com/articles/brain-chip.shtml> [4] B. Rueckauer, C. Bybee, R. Goettsche, Y. Singh, J. Mishra, A. Wild (2021). An API and Compiler for Deep Spiking Neural Networks on Intel Loihi, < https://www.nextplatform.com/2021/01/25/intels-neuromorphic-chip-just-got-more-accessible-for-mainstream-ai/ > [5] ECE6435: Neuromorphic Analog VLSI Circuits course offered at Georgia Tech ECE. [6] Neuromorphic Engineering I and II courses offered at Institute of Neuroinformatics (INI) at the ETH Zurich.

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Aggarwal, A. (2022, August), Neuromorphic VLSI design course Paper presented at 2022 ASEE Annual Conference & Exposition, Minneapolis, MN. 10.18260/1-2--40674

TY - CPAPER
AB - This paper describes a novel Neuromorphic VLSI design course that was added to the Electrical and Computer Engineering curriculum at **** university.
Significance: Neuromorphic VLSI design has been a research area for over 3 decades. It started with attempts to build silicon chips that could emulate functions of various brain regions like eye and cochlea [1]. With Moore’s law hitting physical limits, the industry is looking to improve silicon circuit efficiency by exploring better algorithms like neurally inspired (Neuromorphic). This includes Intel’s foray into building neuromorphic chip, the Loihi [2]. This follows another neuromorphic chip by IBM, the True North [3]. The True North is a neural processor with arrays of neurons and synapses. In addition to being a neural processor, the Loihi chip facilitates learning dynamically like the human brain. These chips can not only be used to emulate areas of the brain but also to build dedicated machine learning hardware [4] and to build neural prosthesis. Despite so many avenues, very few universities offer such a course. Therefore, we decided to offer this course at our university. This course includes teaching low power design, subthreshold mode circuits, mixed-signal chips and combining multiple chips into a system to realize neuromorphic hardware.
Background: Computational elements of neuromorphic circuits are MOSFETs in sub-threshold mode operation. MOSFETs exhibit exponential I-V characteristics and low currents when operating in this mode. Memory is implemented locally within the individual computational elements like floating gates and MITES. These properties lead to the feasibility of high-density, low-power implementation of functions that are computationally intensive in other paradigms.
Curriculum: similar courses at Georgia Tech [5] and at the Institute of Neuroinformatics (INI), ETH Zurich [6] were studied. Based on these, topics studied were: MOS transistors in CMOS technology, floating gates, static circuits, dynamic circuits, systems (silicon neuron-synapse arrays, silicon retina, silicon cochlea, silicon hippocampus, silicon lateral superior olive) with an introduction to multi-chip systems that communicate events analogous to spikes. Course project: building retinal chip circuits and testing them using image data. This course was targeted at seniors and graduate students interested in machine learning, mixed-signal low-power VLSI design and neural engineering. It was a 3-credit lecture course. Grading was based on homework (20%), project (30%), midterm (20%) and final (30%) exams.
Reference materials: Analog VLSI: Circuits and Principles (Shih-Chii Liu, et. al., 2002), Analog VLSI and Neural systems (Carver Mead, 1989), and readings.
Syllabus
Course review
Long term vision
References
[1] Mead, Carver (1989). Analog VLSI and Neural Systems. Addison-Wesley, Reading, MA. ISBN 0201059924.
[2] https://www.intel.com/content/www/us/en/research/neuromorphic-computing.html
[3] D. Modha (2014). Introducing a Brain-inspired Computer TrueNorth's neurons to revolutionize system architecture. < https://research.ibm.com/articles/brain-chip.shtml>
[4] B. Rueckauer, C. Bybee, R. Goettsche, Y. Singh, J. Mishra, A. Wild (2021). An API and Compiler for Deep Spiking Neural Networks on Intel Loihi, < https://www.nextplatform.com/2021/01/25/intels-neuromorphic-chip-just-got-more-accessible-for-mainstream-ai/ >
[5] ECE6435: Neuromorphic Analog VLSI Circuits course offered at Georgia Tech ECE. <https://www.ece.gatech.edu/courses/course_outline/ECE6435>
[6] Neuromorphic Engineering I and II courses offered at Institute of Neuroinformatics (INI) at the ETH Zurich. <https://sites.google.com/view/ne-courses-ini/home?id=start>

AU - Anu Aggarwal
CY - Minneapolis, MN
DA - 2022/08/23
PB - ASEE Conferences
TI - Neuromorphic VLSI design course
UR - https://peer.asee.org/40674
DO - 10.18260/1-2--40674
ER -