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Modeling a Perceptron Neuron Using Verilog Developed Floating-Point Numbering System and Modules for Hardware Synthesis

Conference Session: COED: EE Topics
Collection: 2018 ASEE Annual Conference & Exposition
Authors: Afsaneh Minaie, Utah Valley University; Ephraim Nielson, Utah Valley University
Tagged Divisions: Computers in Education

Relevance Score: 8.82859

Translating the Instructional Processor from VHDL to Verilog

Conference Session: COED: EE Topics
Collection: 2018 ASEE Annual Conference & Exposition
Authors: Ronald J. Hayne, The Citadel
Tagged Divisions: Computers in Education

Relevance Score: 8.82859

Use of FPGAs in a Digital System Design Course with Computer Gaming Applications

Conference Session: COED: EE Topics
Collection: 2018 ASEE Annual Conference & Exposition
Authors: Cheng Chih Liu, University of Wisconsin-Stout
Tagged Divisions: Computers in Education

Relevance Score: 8.82859